Process guys have a lot of variables to play with but two of the biggest are power vs. performance. By which I mean, you can make a low-power device that's slow, or a high-performance device that uses a lot of power. You can't make one transistor that does both - it's a trade-off. Faster switching speeds results in more leakage. If you want to lower leakage, you have to be willing to take a hit in terms of switching speed.
An example of this in CPU's is voltage versus clock frequency. You can lower voltage, which dramatically lowers power, but you pay a cost in terms of frequency which lowers performance.
Another example is this table of 65nm process technology offerings from TSMC:
http://www.tsmc.com/english/b_...tform/b010101_65nm.htm
In this table, you can see general purpose, low power and then high and low Vt process recipes. Low-power transistors will have longer effective channel lengths, and then high Vt gates will have a higher threshold voltage - both of these equate to lower power transistors... but slow.
Using CPU's an example of the power characteristics of modern IC's is problematic because, first, people generally think of desktop CPU's which in which power is only a concern once it reaches a certain threshold (say, 120W) and so it's not something that manufacturers specifically target. But even if you just look at laptop CPU's, even in mobile/laptop CPUs, power and performance play large roles and you can't heavily favor power vs. performance... performance is very important too.
With wireless chips going into portable devices like cell phones, power is generally near the top of the characteristics required. An example, look at Steve Jobs's claim that the first generation iPhone didn't have 3G wireless because the 3G chipsets burn too much power (*). In chips like bluetooth, and 3G and WiMax, power is extremely important. Obviously transmitted power is hard to reduce, but standby power and operational power can be reduced and they generally get lower with each revision of the wireless chipsets as engineers tune the design. So, in the case of wireless chipsets, speed is not the highest priority, power is. So the engineers will use process shifts to lower power while meeting performance goals. With each design iteration, the power dissipation decreases until it hits essentially a lower-limit driven by the transmission requirements. And then when the wireless spec changes, they restart the process with a higher power chipset that gets gradually shrunk and optimized.
So, if you want my answer, the answer is yes, they generally do get lower in power over time - but there are limits below which they are not likely to go, and each new generation of wireless communication chip usually brings with it an increase in performance along with an increase in power.
(*) Steve Jobs: "The 3G chipsets are real power hogs. Handset battery life cuts power to 2-3 hours. Our phone has a talk time of 8 hours and that?s really important when you want to use your phone for internet and music. 3G needs to get back up to 5+ hours, something we think we?ll see later next year. ? WiFi is way faster than any 3G network. Energy efficient EDGE with better, faster WiFi. That?s why we chose it.?
http://www.news.com/8301-13579_3-9780720-37.html