DS1-DS3

YNos

Member
Jan 7, 2002
84
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can anyone point me to a whitepaper of some sort that can explain how a DS1 works, how its MUX'd and De-MUX'd, where it gets its sync times and so on? is it some basterdized rs-485<or any other standard> connection on steroids?
****Or****
Has anyone ever reverse engeneered a Cisco T1 Wic?
they look to be some sort of PCMCIA, but am not sure.
noticing cyclades cards are nasty ~$500 per line, where as these cisco wics are ~$75 on ebay...
would be nice to see how one of these could be setup on a pci adapter.

Craig *yNos* Bailey
 

YNos

Member
Jan 7, 2002
84
0
0
can anyone point me in a direction that might help <w/ the cisco wic, or some whitepapers on larger lines?> i have googled and googled, and still have found any relevant info.
 

Machupo

Golden Member
Dec 15, 1999
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76
www.overclockers-network.com
doesn't DS1/DS3 get it's timing / signalling from the D channel? i seem to remember that the 23B channels at 64kbps each + the D channel + a bit of overhead is where the 1.544Mbps is derived. As for multiplexing, dunno -- try looking up CSU's and DSU's
 

grant2

Golden Member
May 23, 2001
1,165
23
81
If I remember my training correctly, DS1 signal timing is within the signal itself. That is to say, the receiving device uses the voltage changes to synchronize itself with the sender.

This could lead to a problem when there is no voltage change for a long period, which would allow the receiver's timing to drift from the sender. 2 ways to solve this: a, use a protocol which demands a voltage change every X cycles, or b, use a winchester signalling system (which sends data with voltage changes, instead of values values, and thus requires a voltage change every cycle).

Anyways, i may be way off base with all this, and even if not, it doesn't help you much, sorry

 

ScottMac

Moderator<br>Networking<br>Elite member
Mar 19, 2001
5,471
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The "user end" of a T1 usually takes timing from the line.

The line coding for a T1 provides a ~12.5 % ones density to keep the timing at the user end to stay sync'd. The original signaling type was AMI (it's still used in some areas) - AMI = Alternate Mark Inversion .... meaning that within a time slot, there is either a pulse, or not ... if there's a pules it will be the opposite polarity of the pulse before it. If thre are two consecutive pulses of the same polarity, it's considered a "Bi-Polar Violation."

When When T1s started to become popular for data, the ones density rule could be violated, depending on the data (i.e., less than 12.5%). To counter that effect, B8ZS - Binary Eight-Zeros substitution was developed. With B8Zs, anytime thre are eight zeros in a row, the system (CSU/MUX, whatever) removes the zeros and inserts a Bi-Polar Violation (followed by a marker indicating it's intentional). The BPV gives the PLL or receiving timing logic enough ones to stay sync'd.

Signaling within the frame is a different issue (CAS - Channel Associated Signaling), RBS (Robbed Bit Signaling) ....

The "D" channel is used with a PRI (ISDN). ISDN uses a completely different signaling - no robbed bits. While a PRI and T1 both use the same framing and line codes (usually ESF / B8ZS), the actual signaling within the frame is completely different (a T1 and PRI are NOT the same).

The first PRI only uses 23 of the 24 channels (a T1 uses all 24). An advantage with a PRI is that the one 64K D channel from the first PRI can control a number of subsequent PRIs so they can use all 24 channels. In addition, a PRI provides calling party info, data type, and a bunch of other information that is not possible to signal within a T1.


FWIW

Scott

 

grant2

Golden Member
May 23, 2001
1,165
23
81
Great stuff scottmac

Does this mean that PRI is a type of signal that travels over a t1? (like DS1 is a signal that travels over t1).

How many PRIs can be controlled by 1 d-channel?
 
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