Seems pointless to offer a 64K size L2 cache. Its not like its a big change in die size to make it 128K. I wouldn't doubt if its designed with 128K of L2 cache with half of it disabled. Thats the recurring theme in chip design these days...
Originally posted by: MadRat
Seems pointless to offer a 64K size L2 cache. Its not like its a big change in die size to make it 128K. I wouldn't doubt if its designed with 128K of L2 cache with half of it disabled. Thats the recurring theme in chip design these days...
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