[EE|Times] Anayst: IBM "EUV Results Bogus"

[Ajay]

Not all is rosy in EUV Land?

http://www.eetimes.com/document.asp?doc_id=1323353

Also, near the end of the article

In an email exchange, Intel fellow Mark Bohr said his company is already exploring ways to make 7nm chips without EUV. "Intel has a way to achieve good density and good cost-per-transistor on our 10 nm technology without the use of EUV. We are continuing to explore EUV and non-EUV options for our 7nm technology."

 

[krumme]

Note this is old news. Article is from the first of august.
But kind of incredible this pr stunt from ibm gave the stock a boost of 6B. lol.
Also note the NXE3300B used by ibm is now upgraded to NXE3350B and thats the relevant one in comparison to euv as i understand it - or what?
Now technical issues aside my guess its damn difficult in a near monopoly lithography market to get things moving. Add the huge Intel investment prior in asml years back and my guess right now its far from rosy.

About 2012 investment in asml:
http://newsroom.intel.com/community...tion-semiconductor-manufacturing-technologies

 

[krumme]

About the nxe 3350 and the 10nm mid node
http://optics.org/news/5/10/23

And as a little side note about the core m on 14nm:
" which has seen the transistor gate pitch reduced from 90 nm to only 70 nm"

 

[ShintaiDK]

Classic IBM PR.

 

[Ajay]

Note this is old news. Article is from the first of august.
But kind of incredible this pr stunt from ibm gave the stock a boost of 6B. lol.
Also note the NXE3300B used by ibm is now upgraded to NXE3350B and thats the relevant one in comparison to euv as i understand it - or what?
Now technical issues aside my guess its damn difficult in a near monopoly lithography market to get things moving. Add the huge Intel investment prior in asml years back and my guess right now its far from rosy.

About 2012 investment in asml:
http://newsroom.intel.com/community...tion-semiconductor-manufacturing-technologies

Sorry, I wouldn't have made a new thread if I realized it was from August. Even though IBM was using an NXE3300B, they had a 44 watt terminal EUV output (which is around the same as the 3350B, IIRC).

1) It leads me to wonder - how complex are the test dice for the various wafer runs on ASML equipment at partner foundries?

2) Bohr's comment at the end of that article seems to confirm what I though I read before (but couldn't document) - that Intel is really looking at EUVL as a 'possibility' @ 7nm, not @ 10nm.

 

[NostaSeronx]

IBM/GlobalFoundries have dropped EUVL and will be going DSA for the 7-nm node. This news won't be heard till mid-2015 though.

 

[NTMBK]

2) Bohr's comment at the end of that article seems to confirm what I though I read before (but couldn't document) - that Intel is really looking at EUVL as a 'possibility' @ 7nm, not @ 10nm.

I would be astounded if they weren't. When the entire future of the company depends on ASML delivering, you make contingency plans in case something goes wrong. Doesn't mean that they don't still hope to get it sooner.

 

[Ajay]

About the nxe 3350 and the 10nm mid node
http://optics.org/news/5/10/23

And as a little side note about the core m on 14nm:
" which has seen the transistor gate pitch reduced from 90 nm to only 70 nm"

Going from 40 watts currently to 1500 watts (qualified for full CPU/SoC HVM) using EUVL sometime in 2016 is a huge leap in technology. It's not impossible, but it is a pretty bold claim.

 

[witeken]

Not all is rosy in EUV Land?

http://www.eetimes.com/document.asp?doc_id=1323353

Also, near the end of the article

As noted, this is pretty old news although old news is better than missing the news. Your quote seems to be the most important part of the article. There was previously a topic where I held the opinion that Intel would be the company to switch to EUV mid-node at 10nm, but this makes me doubt this because he basically says that they're done with 10nm, it provides good characteristics (cost/transistor, density) and they just need to get it ready for HVM, so they don't have to use EUV.

But maybe he simply didn't want to disclose anything. BTW, I remember Idoncare telling about a EUV conference where we'd get a lot of news, when is that?

 

[Ajay]

I would be astounded if they weren't. When the entire future of the company depends on ASML delivering, you make contingency plans in case something goes wrong. Doesn't mean that they don't still hope to get it sooner.

So this is the part that bothers me. If Intel, which needs to make very complex CPUs/SoCs already has the technology in place to do 10nm with current fab tech (with a xtor density and cost that fits their needs) - why on earth would they tangle with the complexity, validation and costs of retooling 10nm to use EUV?!

That, and the contingency plan is at 7nm, not 10 (which does make more sense to me in terms of the likelihood that EUV with have the output, reliability and uptime necessary for HVM of very complex devices). Intel's volumes at a new node are much higher than anyone else's (as a function of time) - so they, more than anyone else, need to be 99.999% sure that it's going to work.

 

[witeken]

And as a little side note about the core m on 14nm:
" which has seen the transistor gate pitch reduced from 90 nm to only 70 nm"

Mark Bohr already disclosed that, he even explained why they don't reduce gate pitch as much as for example interconnect pitch which is .65 as big.

 

[Ajay]

As noted, this is pretty old news although old news is better than missing the news. Your quote seems to be the most important part of the article. There was previously a topic where I held the opinion that Intel would be the company to switch to EUV mid-node at 10nm, but this makes me doubt this because he basically says that they're done with 10nm, it provides good characteristics (cost/transistor, density) and they just need to get it ready for HVM, so they don't have to use EUV.

Thank you, you made my point better than I did.

But maybe he simply didn't want to disclose anything. BTW, I remember Idoncare telling about a EUV conference where we'd get a lot of news, when is that?

I think that there is an outside chance that Intel is having better success with EUVL than others, in which case Bohr wouldn't want to be talking about that - that, that makes the second part of his statement sound a bit odd.

The Symposium starts today.

 

[Hans de Vries]

Not all is rosy in EUV Land?

http://www.eetimes.com/document.asp?doc_id=1323353

This is complete and udder rubbish from some financial analyst who
apparently got short-squeezed in his portfolio, panicked, and then
tried to stop his financial bleeding by making a lot of insulting ugly
noise on the internet, abusing naive journalists along the way.

Please let us respect the thousands of hardworking engineers who
spend a significant part of their lives making EUV work.

http://electroiq.com/blog/2014/09/beautiful-brilliant-people/
http://electroiq.com/euvl-focus/2014/08/05/thoughts-on-the-significance-of-ibms-euv-benchmark/

 

[Ajay]

This is complete and udder rubbish from some financial analyst who
apparently got short-squeezed in his portfolio, panicked, and then
tried to stop his financial bleeding by making a lot of insulting ugly
noise on the internet, abusing naive journalists along the way.

Please let us respect the thousands of hardworking engineers who
spend a significant part of their lives making EUV work.

http://electroiq.com/blog/2014/09/beautiful-brilliant-people/
http://electroiq.com/euvl-focus/2014/08/05/thoughts-on-the-significance-of-ibms-euv-benchmark/

First. I have a BS in Physics - if I had an advanced degree, I would consider my self blessed to have the opportunity to work on such an interesting and complex problem. So I have no disrespect for hardworking scientists or engineers (I've been both).

Secondly, Semiconductor Advisors LLC specializes in the internal financial analysis of Semiconductor companies. They are do advise investors according to their own web page. If you have additional information, please document it.

Lastly, for IBM's Dan Corliss:

"The parameter settings used for the 24-hour EUV test were established for imaging 22nm dense lines (horizontal and vertical) with a single mask and single exposure," the representative said. "We used 20 mJ/cm2 dose and conventional illumination shape. We did not break the imaging level into multiple masks nor did we employ SMO solutions."

So no resist, no complex mask and only a single pass. It really just a run rate test setting a maximum rate of 600+ wafers/hour. How many passes are going to be required (at 10nm, never mind 7nm) to build up the first layer or two on a wafer? even if it's only 3 passes, we are down to ~200 wafers/day.

One additional item, considering the language used by Corliss, is that I think it's IBM that is looking to insert EUV into their 10nm process (or, I suppose, Global Foundries, at the behest of IBM).

 

[Hans de Vries]

This is complete and udder rubbish from some financial analyst who
apparently got short-squeezed in his portfolio, panicked, and then
tried to stop his financial bleeding by making a lot of insulting ugly
noise on the internet, abusing naive journalists along the way.

Please let us respect the thousands of hardworking engineers who
spend a significant part of their lives making EUV work.

http://electroiq.com/blog/2014/09/beautiful-brilliant-people/
http://electroiq.com/euvl-focus/2014/08/05/thoughts-on-the-significance-of-ibms-euv-benchmark/

Well, maybe we should even pity the poor financial guy...

On July the 16th, 2014 he casts FUD on the possibility of even
illuminating 200 wavers per day with the EUV stepper, accusing ASML
of just using theoretical calculations instead of real numbers. He brags
about being the first to downgrade the stock.

On July the 29th, 2014 then comes the news of IBM illuminating 637
wavers on a single day (originally via a LinkedIn post )


That must be real bad luck for someone who thought he would make
some money by shorting a stock and talking the stock down publicly.

It was good news for everybody else though and another customer has
already repeated it at the end of August.

 

[Ajay]

Well, maybe we should even pity the poor financial guy...

On July the 16th, 2014 he casts FUD on the possibility of even
illuminating 200 wavers per day with the EUV stepper, accusing ASML
of just using theoretical calculations instead of real numbers. He brags
about being the first to downgrade the stock.

On July the 29th, 2014 then comes the news of IBM illuminating 637
wavers on a single day (originally via a LinkedIn post )


That must be real bad luck for someone who thought he would make
some money by shorting a stock and talking the stock down publicly.

It was good news for everybody else though and another customer has
already repeated it at the end of August.

Well, that's sad. You did a better job vetting this guy than EE Times did (and he obviously does more than the web page of his company specifies).


Still, some interesting bits of info about Intel and IBM come out of this thread for those of us in the cheap seats.

 

[swilli89]

For a noob, what is the significance of EUV? And what is the wattage rating mean?

 

[witeken]

For a noob, what is the significance of EUV?

Simply put, if you want smaller transistors, you'll have to use smaller wavelengths of light. In this case, the wavelength will shrink by more than an order of magnitude, which makes things quite a lot easier.

 

[Idontcare]

Classic IBM PR.

FWIW in this case it wasn't really orchestrated IBM PR, rather it was some poor engineer who, after long couple years of being beat on by management to finally hit a milestone or two, took to LinkedIn to merely relay a message of personal achievement for his career at that point. The tech-journo guys caught wind of it and it spread from there.

To be honest I really feel sorry for the IBM guy, he probably thought it was a day of triumph and it turned around and became a matter of public spectacle that bordered on public ridicule.

 

[khon]

The results are not at all bogus.

Noone doubts the imaging capability of EUV, there are plenty of articles on that already, showing that 10/7nm node layers can be done with single exposure. The doubt is on the throughput and stability, which is what the IBM test was intended to prove.

600 wafers in a day is a good step forward, but not enough yet for high volume manufacturing.

 

[khon]

Going from 40 watts currently to 1500 watts (qualified for full CPU/SoC HVM) using EUVL sometime in 2016 is a huge leap in technology. It's not impossible, but it is a pretty bold claim.

Where did you hear 1500W in 2016 ? That is not at all accurate, nor is it needed.

 

[krumme]

Still, some interesting bits of info about Intel and IBM come out of this thread for those of us in the cheap seats.

Same here. Always good to hear eg. Hans de Vries. and IDC but generally i learn a lot each time

 

[krumme]

Where did you hear 1500W in 2016 ? That is not at all accurate, nor is it needed.

I think perhaps Ajay just quickly misread from here - making the 1500 wafers a day to 1500W??:
http://optics.org/news/5/10/23

"A third system has just begun exposing wafers at a customer site, ASML said, and should be included in its sales figures for the closing quarter of calendar 2014 – although true production insertion of EUV for commercial chip manufacturing (requiring throughput of 1500 wafers per day) is still not expected for another two years.

“We are working with a customer towards a mid-node insertion of EUV at the 10 nanometer logic node expected in late 2016,” said ASML’s CEO Peter Wennink. “Other customers are preparing for initial learning in a manufacturing environment.

“In this scenario we expect to ship around six NXE:3350B systems starting mid-2015, on top of the three NXE:3300B systems that will be converted to NXE:3350B configuration.”

In its latest investor presentation, ASML highlighted that it has reached a conversion efficiency of 4 per cent with its laser-driven EUV sources. Source powers of 80 W are said to have been demonstrated internally."

 

[Ajay]

I think perhaps Ajay just quickly misread from here - making the 1500 wafers a day to 1500W??:
http://optics.org/news/5/10/23

So, this is why I don't usually start my own threads. I seem doomed to make more mistakes than usual if I do. I thought 1500 W was high. If I were writing a technical analysis for work - I'd triple check all my facts so that I didn't wind up with egg on my face

 

[Ajay]

The results are not at all bogus.

Noone doubts the imaging capability of EUV, there are plenty of articles on that already, showing that 10/7nm node layers can be done with single exposure. The doubt is on the throughput and stability, which is what the IBM test was intended to prove.

600 wafers in a day is a good step forward, but not enough yet for high volume manufacturing.

Thanks for the info. I though there were still some issues with the masks, because of EUVL mask defect sensitivity. As far as the number of exposures, I was still using numbers from multi-patterning - my bad. One of the major points of EUV is the reduction in manufacturing steps (exposure, etch, dep, ect.).