Good question.
Intel indeed doesn't make the tools they use to make the chips themselves. They use ASML for lithography and other companies like Applied Materials.
Read:
Beyond 22nm: Applied Materials, the unsung hero of Silicon Valley
All those companies deliver the necessary tools, but you have to tweak them because you start at 0 yields.
Furthermore, Intel's lithography advantage isn't that big. At the same node, Intel was (up to 14nm) actually less dense, but their TTM was about 2 years or so faster, so that was about the same. At 16nm, however, TSMC is just going to recycle their 20nm node and put FinFET transistors in it instead. Because TSMC will pause more than 1 year to do so, Intel's will have a even bigger density lead as well as a density lead at iso node name.
But density isn't everything. If you have those tools, you can't suddenly make a FinFET with great characteristics. Those technologies like HKMG, strained silicon and Tri-Gate have to be researched, and Intel has had a lead of about 3.5 years for strained silicon and HKMG. If TSMC hadn't pulled in FinFET at their 20nm node, Intel's lead would have been 6 years or so.
So: Intel's density/lithography lead isn't that big (but this is for a big part because Intel didn't need the highest densities but highest performance), but their R&D on how they make the transistors with those tools has a massive lead, and probably their yields as well.
Edit: also worth reading:
http://forums.anandtech.com/showpost.php?p=36515598&postcount=10
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Unrelated to the above, I'd like to ask following question: do you think EUV would've reached HVM health sooner if there was more lithography competition than only ASML?