[EE|Times] Anayst: IBM "EUV Results Bogus"

[III-V]

For a noob, what is the significance of EUV? And what is the wattage rating mean?

EUV is extremely significant. It's the successor to the current ArF lithography, which we've been using for well over ten years. The plans for ArF's initial successor, CaF2 or F2, fell through, so they've had to stick with ArF for a lot longer than planned, especially given that EUV was initially planned to be introduced somewhere around 5 years ago.

To manufacture current state of the art chips, they're having to do multiple exposures of ArF litho, which is expensive. Still, they're managing to reduce transistor costs by a factor of two every two years (ish), but EUV will make that easier.

Basically, chip costs will come down a lot, as a result.

 

[swilli89]

EUV is extremely significant. It's the successor to the current ArF lithography, which we've been using for well over ten years. The plans for ArF's initial successor, CaF2 or F2, fell through, so they've had to stick with ArF for a lot longer than planned, especially given that EUV was initially planned to be introduced somewhere around 5 years ago.

To manufacture current state of the art chips, they're having to do multiple exposures of ArF litho, which is expensive. Still, they're managing to reduce transistor costs by a factor of two every two years (ish), but EUV will make that easier.

Basically, chip costs will come down a lot, as a result.

Ah OK thank you very much. Seems like this is part of the reason we've been stuck at "28nm" for so long.

 

[III-V]

Ah OK thank you very much. Seems like this is part of the reason we've been stuck at "28nm" for so long.

Yep, that's definitely a big factor.

 

[witeken]

EUV is extremely significant.

Certainly if you want III-V semiconductors. Pun intended.

Still, they're managing to reduce transistor costs by a factor of two every two years (ish), but EUV will make that easier.

More like a factor sqrt(2).

Basically, chip costs will come down a lot, as a result.

I doubt it. The lower cost will be used to use more transistors to make them faster and/or use the higher margins to research and develop better technology.

 

[Roland00Address]

For a noob, what is the significance of EUV? And what is the wattage rating mean?

This is simplifying it tremendously, but from one noob to another who is in awe of all the work these engineers and scientists do, I will try my best to simplify.


As was already mentioned EUV / EUVL allows smaller wavelengths of light to be used with lithography (the more red the longer the wavelength the more blue and violet it is the shorter the wavelength). Smaller wavelengths means higher details, this allows more transistors per wafer and hopefully better performing transistors.

Lithography is kinda like having a negative for film (the mask) shining it on special materials which will etch and change the underlying material and imprint the design you want onto it. Think of it like making a photo from a negative onto special photo paper in a dark room.

Now the higher the wattage the less time it takes to etch a single exposure (just like a hotter and more intense flame melts wax faster). A higher wattage may also mean it is possibly to do the same work with less exposures. A higher wattage means you can do more wafers per day and thus make more money.

Thus the engineering problem of increasing the wattage is a very big deal. We already solved some of the scientific problems of making such fine details but implement it in a reality on a mass scale is a both a science and engineering challenge.

 

[pw257008]

I doubt it. The lower cost will be used to use more transistors to make them faster and/or use the higher margins to research and develop better technology.

Well, in the second case, it would still reduce cost/chip on the fab side (at least from a variable cost perspective), but maybe not long run costs if R&D costs increase proportionately, and maybe not on the pass through to the processor manufacturer (even including Intel's non-fab side, assuming that R&D goes to the fab) and eventually consumers. And the first case isn't reducing chip costs necessarily, but it would reduce cost/performance, which is really what matters on consumer side.

 

[videogames101]

This is simplifying it tremendously, but from one noob to another who is in awe of all the work these engineers and scientists do, I will try my best to simplify.


As was already mentioned EUV / EUVL allows smaller wavelengths of light to be used with lithography (the more red the longer the wavelength the more blue and violet it is the shorter the wavelength). Smaller wavelengths means higher details, this allows more transistors per wafer and hopefully better performing transistors.

Lithography is kinda like having a negative for film (the mask) shining it on special materials which will etch and change the underlying material and imprint the design you want onto it. Think of it like making a photo from a negative onto special photo paper in a dark room.

Now the higher the wattage the less time it takes to etch a single exposure (just like a hotter and more intense flame melts wax faster). A higher wattage may also mean it is possibly to do the same work with less exposures. A higher wattage means you can do more wafers per day and thus make more money.

Thus the engineering problem of increasing the wattage is a very big deal. We already solved some of the scientific problems of making such fine details but implement it in a reality on a mass scale is a both a science and engineering challenge.

Simply, the resolution for a lithography system is directly related to the wavelength of light you use:

CD is your critical dimension, NA and k are practically limited values related to the lens and surrounding process, so wavelength is very important. I'm not familiar with the problems of EUV, but this is the reason it's valuable for continued reduction of feature size. There are tricks to getting better resolution with the same wavelength, phase masks, multi-patterning, etc. but they all cost money (and even more so design time) that hopefully EUV eventually won't.

For the guy who was asking, see "Resolution in projection systems" Wikipedia for this and more information.

 

[III-V]

I doubt it. The lower cost will be used to use more transistors to make them faster and/or use the higher margins to research and develop better technology.

Well sure, but it totally depends on the business model. It'll enable higher performance, higher performance/dollar, or lower costs, depending on how it's leveraged by each new design.

 

[Lepton87]

EUV is extremely significant. It's the successor to the current ArF lithography, which we've been using for well over ten years. The plans for ArF's initial successor, CaF2 or F2, fell through, so they've had to stick with ArF for a lot longer than planned, especially given that EUV was initially planned to be introduced somewhere around 5 years ago.

What was the planed wavelength of those CaF and F light sources and why didn't it work at all?

 

[NostaSeronx]

What was the planed wavelength of those CaF and F light sources and why didn't it work at all?

It's the requirement of having a vacuum.

http://en.wikipedia.org/wiki/Vacuum

 

[Idontcare]

What was the planed wavelength of those CaF and F light sources and why didn't it work at all?

157nm litho, the planned successor to 193nm litho, hit a snag when it was discovered (well into the development cycle mind you) that CaF2 had birefringence that essentially made it unusable as an optical material for all practical purposes.

It was a "gotcha" moment for the industry, I had a front row seat to it and I can vividly remember the day this was announced as it made ripples throughout the industry.

http://www.eetimes.com/document.asp?doc_id=1175202

The fallback was to keep with 193nm litho but go with immersion as a means to increase the numerical aperture (NA) which decreases the effective wavelength of the photons.

A 193nm photon is only 193nm in a vacuum where the refractive index is 1 (unity). Put that 193nm photon into water, where the refractive index is approximately 1.44 (it varies by wavelength of the photon and the purity of the water), and the photon shrinks in wavelength to 193nm/1.44 = 134nm.

So this is why they can still use 193nm litho to print smaller and smaller features, the photons themselves are effectively becoming smaller as they make the R.I. of the immersion medium higher and higher, as well as improving the resolution of the optical chain itself by increasing the numerical aperture.

The fallback solution to having EUV is to simply continue identifying higher R.I. mediums that can be leveraged to continue to extend 193nm immersion for future nodes.

 

[Ajay]

Cool, the lenses for those light sources created polarity differentiated refractive indices - science is way cool and sometimes a PITA. Thanks for that link!

I wonder what immersion medium fabs are using for sub 22nm? The whole system must be tweaked to the max - multiple computational masks for multi-patterned exposures and sub nano-meter level registration - oh my!

 

[videogames101]

157nm litho, the planned successor to 193nm litho, hit a snag when it was discovered (well into the development cycle mind you) that CaF2 had birefringence that essentially made it unusable as an optical material for all practical purposes.

It was a "gotcha" moment for the industry, I had a front row seat to it and I can vividly remember the day this was announced as it made ripples throughout the industry.

http://www.eetimes.com/document.asp?doc_id=1175202

The fallback was to keep with 193nm litho but go with immersion as a means to increase the numerical aperture (NA) which decreases the effective wavelength of the photons.

A 193nm photon is only 193nm in a vacuum where the refractive index is 1 (unity). Put that 193nm photon into water, where the refractive index is approximately 1.44 (it varies by wavelength of the photon and the purity of the water), and the photon shrinks in wavelength to 193nm/1.44 = 134nm.

So this is why they can still use 193nm litho to print smaller and smaller features, the photons themselves are effectively becoming smaller as they make the R.I. of the immersion medium higher and higher, as well as improving the resolution of the optical chain itself by increasing the numerical aperture.

The fallback solution to having EUV is to simply continue identifying higher R.I. mediums that can be leveraged to continue to extend 193nm immersion for future nodes.

Seems surprising someone didn't recognize that in the research phase.

 

[swilli89]

This is simplifying it tremendously, but from one noob to another who is in awe of all the work these engineers and scientists do, I will try my best to simplify.


As was already mentioned EUV / EUVL allows smaller wavelengths of light to be used with lithography (the more red the longer the wavelength the more blue and violet it is the shorter the wavelength). Smaller wavelengths means higher details, this allows more transistors per wafer and hopefully better performing transistors.

Lithography is kinda like having a negative for film (the mask) shining it on special materials which will etch and change the underlying material and imprint the design you want onto it. Think of it like making a photo from a negative onto special photo paper in a dark room.

Now the higher the wattage the less time it takes to etch a single exposure (just like a hotter and more intense flame melts wax faster). A higher wattage may also mean it is possibly to do the same work with less exposures. A higher wattage means you can do more wafers per day and thus make more money.

Thus the engineering problem of increasing the wattage is a very big deal. We already solved some of the scientific problems of making such fine details but implement it in a reality on a mass scale is a both a science and engineering challenge.

I like your imagery. I have another question. Since I've been following CPU/GPU developments to smaller nodes (since around Pentium Coppermine and Athlon Thunderbird days) I have always just sort of assumed that Intel/AMD(GF)/IBM basically made the process that they themselves used. This company that is shipping "NXE:3350B's", are these the machines that actually perform the lithography? And if so that leads me to my next question,

If Intel is buying the machines that it makes its chips with, how does Intel have such a dominant process lead?

 

[Idontcare]

Seems surprising someone didn't recognize that in the research phase.

That degree of a snafu was rather unsettling, but that specific era of semicon research was fraught with them.

Another example is the low-k dielectric "SiLK" in which IBM went all the way to ramping volume production with Xilinx before they recognized that it was simply not manufacturable (it had absolutely abysmal mechanical strength, which made the devices have really bad reliability in the field).

Altera pounces as Xilinx becomes latest to abandon low-k SiLK: Rivals scrap in dielectric flap

False starts happen often in research, in my opinion Intel has perhaps the best pipeline (via their pathfinding program) in the industry in terms of vetting R&D options before seriously pursuing them as development options.

(they were the first to abandon 157nm litho, for example)

 

[Idontcare]

I like your imagery. I have another question. Since I've been following CPU/GPU developments to smaller nodes (since around Pentium Coppermine and Athlon Thunderbird days) I have always just sort of assumed that Intel/AMD(GF)/IBM basically made the process that they themselves used. This company that is shipping "NXE:3350B's", are these the machines that actually perform the lithography? And if so that leads me to my next question,

If Intel is buying the machines that it makes its chips with, how does Intel have such a dominant process lead?

Before the mid-to-late 80's, semicon manufacturers did infact make their own equipment (generically called "tools" in the industry).

In the late 80's it became all the rage to spin-out your internal tool development division as a means to "unlock shareholder value". In other words the IDMs started the process of becoming less and less vertically integrated.

Nowadays no one makes their own tools, they buy them from tool vendors such as ASML.

The CPU manufacturers still control the processes that are used on the tools. (called "recipes" in the industry)

So even though two companies might buy the exact same tool, they will use them in very different ways as they optimize the processes ran on the tools differently from each other.

 

[swilli89]

Before the mid-to-late 80's, semicon manufacturers did infact make their own equipment (generically called "tools" in the industry).

In the late 80's it became all the rage to spin-out your internal tool development division as a means to "unlock shareholder value". In other words the IDMs started the process of becoming less and less vertically integrated.

Nowadays no one makes their own tools, they buy them from tool vendors such as ASML.

The CPU manufacturers still control the processes that are used on the tools. (called "recipes" in the industry)

So even though two companies might buy the exact same tool, they will use them in very different ways as they optimize the processes ran on the tools differently from each other.

Thank you.. "unlocking shareholder value" sounds like a buzz phrase I had to learn early in business school. I guess divesting something you don't want as a core competency makes sense if you're going to plan on excelling at creating "recipes".

So now knowing that, I would say a company like Intel has 2 main proficiencies, crafting process recipes on 3rd party tools and designing transistor logic for their own products. Would you agree or is there another large step in the process of making computing chips?

 

[krumme]

Thanx for great posts IDC!

Under the asumption Intel have better ways to control immersion in a high capacity production environment, thereby altering the NA value, it makes perfect sense if they dont persue EUV as fast now. But wait and let the others do the learning and take the risk. They need it more. IMO it just shows how comfortable position Intel is in - at present.

If we look at what is selling on the market, what drives the need for lesser nodes now is the mobile side. Its apple and Samsung high-end phones driving need - thats where 20nm is going now and probably 16nm versions in a year. Intels venture into that market is not going well, and i think its fair to say there is next to zero chance of a 14nm apple or samsung product fall 2015 in the main selling products.
At the same time eg. the serverline is generating tons of profit on relatively old designs and processes. Intel have plenty room the accelerate here if it was needed even without new processes.

In that situation - why speed up EUV - that will mainly help your competitors?

Add. its cost, and we have seen Intel reduce their capex.

Now they might get late to EUV. And yes, as we discussed weeks ago, Seronx is probably right that for 10nm density will then suffer. But the upside is reduced developing cost. Reduced risk (and that could turn into a huge winner). And also your competitors will get EUV later. So while Intel - on paper - might lose some technological advantage they used to have, they have gained a less risk approach and a cost advantage.

 

[witeken]

I like your imagery. I have another question. Since I've been following CPU/GPU developments to smaller nodes (since around Pentium Coppermine and Athlon Thunderbird days) I have always just sort of assumed that Intel/AMD(GF)/IBM basically made the process that they themselves used. This company that is shipping "NXE:3350B's", are these the machines that actually perform the lithography? And if so that leads me to my next question,

If Intel is buying the machines that it makes its chips with, how does Intel have such a dominant process lead?

Good question.

Intel indeed doesn't make the tools they use to make the chips themselves. They use ASML for lithography and other companies like Applied Materials.

Read: Beyond 22nm: Applied Materials, the unsung hero of Silicon Valley

All those companies deliver the necessary tools, but you have to tweak them because you start at 0 yields.

Furthermore, Intel's lithography advantage isn't that big. At the same node, Intel was (up to 14nm) actually less dense, but their TTM was about 2 years or so faster, so that was about the same. At 16nm, however, TSMC is just going to recycle their 20nm node and put FinFET transistors in it instead. Because TSMC will pause more than 1 year to do so, Intel's will have a even bigger density lead as well as a density lead at iso node name.

But density isn't everything. If you have those tools, you can't suddenly make a FinFET with great characteristics. Those technologies like HKMG, strained silicon and Tri-Gate have to be researched, and Intel has had a lead of about 3.5 years for strained silicon and HKMG. If TSMC hadn't pulled in FinFET at their 20nm node, Intel's lead would have been 6 years or so.

So: Intel's density/lithography lead isn't that big (but this is for a big part because Intel didn't need the highest densities but highest performance), but their R&D on how they make the transistors with those tools has a massive lead, and probably their yields as well.

Edit: also worth reading: http://forums.anandtech.com/showpost.php?p=36515598&postcount=10

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Unrelated to the above, I'd like to ask following question: do you think EUV would've reached HVM health sooner if there was more lithography competition than only ASML?

 

[Idontcare]

-------
Unrelated to the above, I'd like to ask following question: do you think EUV would've reached HVM health sooner if there was more lithography competition than only ASML?

Yes, but only at the expense of vastly less efficient use of R&D dollars as an industry as a whole.

The resultant EUV tools would have been all the more expensive, factoring in the elevated amortization, which would have made the barrier to entry in the EUV market higher than it already is.

Competition is good at driving the pace of innovation, but it is an inefficient mechanism (R&D expenditures summed across a given industry) for generating the innovation.

That is why consortiums were created, to more efficiently use the industry's R&D dollars inventing just one or two wheels instead of having everyone re-invent the same wheel 10 times over.

In many ways, EUV was clearly something too big for the industry to tackle, the jump was too much.

They really should have opted for something less aggressive than 13.5nm for the same reasons they didn't attempt to go from the 180nm process node to the 14nm process node in one single step.

 

[MisterMac]

Yes, but only at the expense of vastly less efficient use of R&D dollars as an industry as a whole.

The resultant EUV tools would have been all the more expensive, factoring in the elevated amortization, which would have made the barrier to entry in the EUV market higher than it already is.

Competition is good at driving the pace of innovation, but it is an inefficient mechanism (R&D expenditures summed across a given industry) for generating the innovation.

That is why consortiums were created, to more efficiently use the industry's R&D dollars inventing just one or two wheels instead of having everyone re-invent the same wheel 10 times over.

In many ways, EUV was clearly something too big for the industry to tackle, the jump was too much.

They really should have opted for something less aggressive than 13.5nm for the same reasons they didn't attempt to go from the 180nm process node to the 14nm process node in one single step.

IDC Posts always make you feel warm & fuzzy inside! :thumbsup:

 

[swilli89]

Good question.

Intel indeed doesn't make the tools they use to make the chips themselves. They use ASML for lithography and other companies like Applied Materials.

Read: Beyond 22nm: Applied Materials, the unsung hero of Silicon Valley

All those companies deliver the necessary tools, but you have to tweak them because you start at 0 yields.

Furthermore, Intel's lithography advantage isn't that big. At the same node, Intel was (up to 14nm) actually less dense, but their TTM was about 2 years or so faster, so that was about the same. At 16nm, however, TSMC is just going to recycle their 20nm node and put FinFET transistors in it instead. Because TSMC will pause more than 1 year to do so, Intel's will have a even bigger density lead as well as a density lead at iso node name.

But density isn't everything. If you have those tools, you can't suddenly make a FinFET with great characteristics. Those technologies like HKMG, strained silicon and Tri-Gate have to be researched, and Intel has had a lead of about 3.5 years for strained silicon and HKMG. If TSMC hadn't pulled in FinFET at their 20nm node, Intel's lead would have been 6 years or so.

So: Intel's density/lithography lead isn't that big (but this is for a big part because Intel didn't need the highest densities but highest performance), but their R&D on how they make the transistors with those tools has a massive lead, and probably their yields as well.

Edit: also worth reading: http://forums.anandtech.com/showpost.php?p=36515598&postcount=10

-------
Unrelated to the above, I'd like to ask following question: do you think EUV would've reached HVM health sooner if there was more lithography competition than only ASML?

The link you shared was an excellent read for anyone else interested

 

[Ajay]

In many ways, EUV was clearly something too big for the industry to tackle, the jump was too much.

They really should have opted for something less aggressive than 13.5nm for the same reasons they didn't attempt to go from the 180nm process node to the 14nm process node in one single step.

True, but as seen with 157nm light, once you start to move away from glass for refraction, you run into materials that have wavelength dependent aberrant optical behavior (even in the choice reflector materials). It seems to me that the semicon industry would have used EUV eventually, and by avoiding a cascade of pathfinding R&D for varying light sources and transmission systems, they could put all there eggs in one, very expensive, basket.

The downside, of course, is that EUV, technically, should have been here for 14nm as a minimum, but it wasn't. This cause a great deal of difficulty for the largest on most capable chip manufacturer. It seems, at this point, that EUV is almost inevitable, but that Intel is wary enough about reaching it's desired wafer throughput and system up-time that it's pursuing two paths for 7nm production.

PS Thanks for the great input on this thread topic.

 

[Lepton87]

They really should have opted for something less aggressive than 13.5nm for the same reasons they didn't attempt to go from the 180nm process node to the 14nm process node in one single step.

Thanks for the earlier answer. Why exactly 13.5nm wavelength was chosen and what were the alternatives? Surely it must have made sense at the time.

 

[Idontcare]

Thanks for the earlier answer. Why exactly 13.5nm wavelength was chosen and what were the alternatives? Surely it must have made sense at the time.

13.5nm was chosen for a number of technical, development cost, timeline, and risk management reasons. But it certainly wasn't the only option.

What has come quite clear is that all of those reasons were improperly targeted or estimated. Everyone underestimated the true development timeline, cost, and risk when selecting 13.5nm as the targeted wavelength.

Had they to do it all over again, there is no doubt they would have gone with a less aggressive wavelength on a more manageable timeline and development budget.

Shooting for 13.5nm made sense at the time because at the time immersion litho and multi-patterning made no technical or economic sense, and because everyone was told to have faith and believe the R&D roadmap would make it all magically happen in a timeline that would make going for something easier and less aggressive be a pointless exercise.

It turned out to be too good to be true, and here we are a decade later still waiting for EUV to deliver on the promised goods