Well that approach sounds ok, first you set your goal, then you look for the best and cheapest way to reach that goal.
But why would you change it mid-way again? Like intel from 16->14, and according to eetimes the SOI-consortium from 20 to 14? New marketing guys?
But GF still has the "normal" 20nm process, thus I wonder now if it is really a rename from the SOI-people or not. Let's wait and see.
They likely found they had set their initial targets to conservatively. I lived through that happening myself once.
For 65nm at TI we initially set our shrink targets such that we anticipated needing a metal 1 pitch of 210nm, representing a 77.78% linear shrink over our 90nm process (which had a 270nm M1 pitch)...only we discovered about a year into development that 210nm was way too easy to achieve with yield entitlement, we hadn't set out goals aggressive enough and as such we were meeting all of our R&D milestones well ahead of schedule in every way.
So we went back and shrunk everything by another 5% linearly, setting the M1 pitch to 200nm. Still was too easy to reduce to practice (if you can call it "easy" ), yields were silly high and xtors were coming into target way too easily given our production schedule.
So we went back and gave ourselves a third stretch goal, with an additional 10% linear shrink, netting a M1 pitch of just 180nm.
At 180nm our 65nm process was coming in with a 66.7% linear shrink factor compared to the existing 90nm process, a rather unprecedented 44.4% areal footprint for logic (well ahead of the typical 60% areal shrink for logic).
Technically our 65nm should have been relabled something along the lines of 60nm or 55nm, or perhaps our 90nm should have never been named 90nm (maybe it should have been 95 or 100nm).
Regardless the naming justification, we opted to keep with the existing node label even though every single design rule and electrical parametric was being shifted around with the ensuing changes.
I suspect Intel experienced a similar situation in which their initial targets for the post-22nm shrink had them feeling that a 16nm node label was appropriate, but they found the development was actually easier than anticipated, breakthroughs were coming faster and better, well ahead of schedule.
So they went back and instead of bringing out 16nm sooner, ahead of schedule, they would make the shrink goals even more challenging (with higher reward then when it goes to production) and they likewise decided a numerically smaller node label was called for at the same time.