EETimes: ST plans for Dresden FDSOI production

[MisterMac]

Extremely far apart. Just as AMD and IBM were completely caught off-guard by Intel's aggressive development and adoption of HKMG into production at 45nm, they were even more caught off-guard by the development and adoption of FinFet into production at 22nm.

So what you saw, and continue to see, is IBM and GloFo operating in crisis mode, rushing under-developed process technologies through the R&D pipeline and making ill-advised tradeoffs in the process (bad 32nm dielectric decisions, gate first decision, 28nm disaster, etc).

And they are continuing that tradition with Finfet and 14nm...rushing an underperforming FinFet product (it can only manage enough Idrive to power mobile devices without burning itself up, if they try and power it with enough current and voltage to hit GHz speeds needed for CPUs and GPUs then it dies very quickly) to market for 20nm but re-labeling it a 14nm-XM product because they can't figure out how to rush the 14nm BEOL (metal wiring) to market at the same time.

The gap between Intel and GloFo continues to grow, we see it in their limited release of Finfet for 14nm (mobile only, not high performance) and the lack of scaling in the BEOL. GloFo's 14nm-XM customers will be ill-equipped to field cost or performance competitive parts if those customers are competing with Intel or high-performance customers of TSMC.

Even though TSMC is doing the same shenanigans with the BEOL not shrinking to 16nm, at least they have do intend to field finfet transistors that are robust enough to function (and survive) in the higher voltage and current environment that comes with the MPU version of their 16nm node.

It is difficult to see a silver lining in GloFo's looming dark clouds TBH. Their technology roadmap is not competitive even if they manage to pull it off without delays the likes of which 32nm and 28nm have experienced

So the tradeoff that GloFo does - is not being able to manufacture IP designs in a "sturdy\robust way" which makes the IP less able to achieve clocks and less able to not fall apart at high electrical current.

...but will have a product line that is label wise attractive?

What about TSMC? and their 20nm? Is the gap also big from Intel?

Can TSMC actually design HP lines like for x86 or 500mm die gpu's on 20 nm next year - and will yields be enough to release products?


Obviously by your own personal estimates - cause the marketing seems to suggest that intel's advantage is shrinking ... in the wider public sense.

(PS THANKS!).

 

[Phynaz]

More extraordinary claims from GloFo...

Extraordinary certainly is the correct word.

 

[SocketF]

GF's yields were presented yday (a bit):

a) HK-yields, I guess that's AMD's Fusion & FX-Chips / 32nm

b) SRAMs@low-power nodes @28nm

Sorry for the blurry pics, they are directly from the webcast. You can see that there are years on the x-axis 2011 and 2012, then no data points for 2013-2015.

 

[Idontcare]

Partly explains why 28nm hasn't happened yet, D0 > 0.2 is considered not good.

 

[SocketF]

Partly explains why 28nm hasn't happened yet, D0 > 0.2 is considered not good.

How would you define the initial 1.2 for HPP and the initial 0.6 for the HPP "complex HKMG product?

Catastrophic and half catastrophic? :ninja:

I wonder if it was because of gate first something else and if that "complex product" was AMD's canceled Krishna-Bobcat.

 

[Idontcare]

How would you define the initial 1.2 for HPP and the initial 0.6 for the HPP "complex HKMG product?

Catastrophic and half catastrophic? :ninja:

I wonder if it was because of gate first something else and if that "complex product" was AMD's canceled Krishna-Bobcat.

Those are typical D0 values in the final year of a node's development. Pre-production.

But don't look at those numbers as "initial"...they chose to not publicly show the data collected before those points on the graph but the data exists.

Consider that the only reason they publicly disclose information like this is to build confidence in existing and would-be customers that GloFo knows what the heck it is doing.

Any data that might not support that confidence building effort is going to be scrubbed from the presentations and ignored by the presenter(s). That's just basic marketing at work.

If they really wanted to boost confidence though they wouldn't show data on something that was supposed to be in production 1-2 yrs ago, rather they should have shown data that spoke to the health of their currently under-development nodes. Show D0 progress for 20nm.

 

[Hitman928]

If they really wanted to boost confidence . . . they should have shown data that spoke to the health of their currently under-development nodes. Show D0 progress for 20nm.

I'm not so sure that would have built confidence though

 

[SocketF]

Any data that might not support that confidence building effort is going to be scrubbed from the presentations and ignored by the presenter(s). That's just basic marketing at work.

If they really wanted to boost confidence though they wouldn't show data on something that was supposed to be in production 1-2 yrs ago, rather they should have shown data that spoke to the health of their currently under-development nodes. Show D0 progress for 20nm.

Hhaha, that's soo true .. what do we want with numbers about a process that is - according to some old roadmaps - ready since 2011

 

[mrmt]

If they really wanted to boost confidence though they wouldn't show data on something that was supposed to be in production 1-2 yrs ago, rather they should have shown data that spoke to the health of their currently under-development nodes. Show D0 progress for 20nm.

What if they are targeting a market like the 2nd tier customers like UMC is doing? Then the confidence building effort for 28nm would make sense.

 

[Idontcare]

What if they are targeting a market like the 2nd tier customers like UMC is doing? Then the confidence building effort for 28nm would make sense.

That's a good point. The one weakness with TSMC being your foundry is that as a fabless company all your eggs are in one basket.

Qualcomm for example, huge company that is one Taiwan earthquake away from having zero supply of 28nm chips.

The advantage of GlobalFoundries is, in theory, you can have Europe and N.America supplies of 28nm chips. If catastrophe strikes a region with one of those fabs then at least you have chips still coming from the other one. Not ideal but not a total catastrophe either.

 

[Idontcare]

Globalfoundries commits to FDSOI process

Mike Noonen, executive vice president of worldwide marketing and sales at the foundry chip maker, told an audience at the Common Platform Technology Forum, held at the Santa Clara Convention Center, California, that a physical design kit for the process will be available in the first quarter of 2013. The first "risk production" will come from a Globalfoundries wafer fab in 4Q13 and volume production will ramp during the first half of 2014, Noonen said.

Noonen stressed the ease of transition to FDSOI from bulk CMOS as well as some of the advantages. "About 80 percent of the front-end of line is the same as 28LP/28SLP. The back-end of line is pretty much identical to the 28LP/28SLP platform. There is IP reuse from bulk," he said, referring to Globalfoundries' bulk planar CMOS manufacturing processes at 28-nm. He added that the ability to use back-biasing of the wafer allows a speed boost for ICs made using the process.

http://www.eetimes.com/design/eda-design/4406513/GloFo-commits-to-FDSOI

The focus seems to be on LP and SLP with absolutely no mention of being used for the HP or HPP processes. That would rule out any possible use by AMD for x86 or discete GPU products IMO.

 

[mrmt]

The focus seems to be on LP and SLP with absolutely no mention of being used for the HP or HPP processes. That would rule out any possible use by AMD for x86 or discete GPU products IMO.

Looks like that GLF is committed to 2nd and 3rd tier customers.

 

[Phynaz]

Looks like that GLF is committed to 2nd and 3rd tier customers.

Not at all. LP is a very large part of the chip market. You're thinking is narrow minded when thinking the high performance pc market is the only top tier market.

 

[mrmt]

Not at all. LP is a very large part of the chip market. You're thinking is narrow minded when thinking the high performance pc market is the only top tier market.

No, the rationale is not that. 1st tier customers are already committed to TSMC roadmap, which means 20nm bulk and 14nm bulk finfet. By fielding 28nm SOI now, they are probably trying to attract 2nd and 3rd tier customers that didn't jump the 28nm bandwagon with TSMC or UMC.

 

[SocketF]

The focus seems to be on LP and SLP with absolutely no mention of being used for the HP or HPP processes. That would rule out any possible use by AMD for x86 or discete GPU products IMO.

No, FD-SOI's LP heritage is well known since long ago, because of back biasing this is not a problem. See the clock-scaling graph in the 2nd link:

More on the LP-HP-FD-SOI differences here:

http://blog.stericsson.com/blog/201...st-ericssons-next-generation-novathor-part-1/

http://blog.stericsson.com/blog/2012/05/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-%E2%80%93-part-2-2/

There you can see that FD-SOI, even though it is based on LP-libraries is able to compete with the 28nm HP-process.

Concerning FD-SOI, Noonen didn't say anything new.

 

[Idontcare]

No, FD-SOI's LP heritage is well known since long ago, because of back biasing this is not a problem. See the clock-scaling graph in the 2nd link:


There you can see that FD-SOI, even though it is based on LP-libraries is able to compete with the 28nm HP-process.

Concerning FD-SOI, Noonen didn't say anything new.

Why would Noonen be so explicit in referring to LP/SLP to the exclusion of HP and HPP?

Had he not qualified his comments so pointedly, had he simply spoke generically to 28nm, then I would be more readily convinced.

But he went to efforts to speak of FD-SOI in limited comparison to only the LP and SLP sub-nodes. That means something, unless we assume he misspoke (and more than once), which would be odd in its own right.

 

[SocketF]

Why would Noonen be so explicit in referring to LP/SLP to the exclusion of HP and HPP?

Because the process is based on LP/SLP, mentioning HP/P would simply be wrong.

Had he not qualified his comments so pointedly, had he simply spoke generically to 28nm, then I would be more readily convinced.

But he went to efforts to speak of FD-SOI in limited comparison to only the LP and SLP sub-nodes. That means something, unless we assume he misspoke (and more than once), which would be odd in its own right.

Well because of the used (S)LP base, the preliminary aim is of course also the same market. However, as eetimes also said it:

"About 80 percent of the front-end of line is the same as 28LP/28SLP. The back-end of line is pretty much identical to the 28LP/28SLP platform. There is IP reuse from bulk," he said, referring to Globalfoundries' bulk planar CMOS manufacturing processes at 28-nm. He added that the ability to use back-biasing of the wafer allows a speed boost for ICs made using the process.

I don't see any problems, the characteristics from STE's blog entry have not changed. FD-SOI gives you less leakages than HP because of its LP base, but also enables high clocks compareable to HP-processes by allowing higher core-voltages than the usual LP-process by using back bias.

I guess normal LP-customers are not interested in higher-clocks, they really only focus on low-power.

 

[mrmt]

Because the process is based on LP/SLP, mentioning HP/P would simply be wrong.

If I had a LP/SLP process that could go head to head with my competitor's HP/HPP on performance and costs, I would go on record and and say exactly this and would invite every HP/HPP possible to make risk production runs with me ASAP, and not just point out how easy is to port to my HP/HPP FDSOI from bulk and mention LP/SLP as my TAM.

 

[NostaSeronx]

the focus seems to be on lp and slp with absolutely no mention of being used for the hp or hpp processes.

FD-SOI equals SHP.

 

[Phynaz]

FD-SOI equals SHP.

Lol, no.

 

[AtenRa]

I dont see 28nm HP/SHP FD-SOI in the near future from AMD. It is clear that 28nm LP/SLP FD-SOI is targeting ARM, FPGAs and more SoCs than High Performance Chips like CPUs/GPUs.

 

[Gideon]

Theoretically A Temash successor could benefit from FD-SOI, provided AMD is stuck with Glo-Fo and would otherwise have to use "vanilla" 28nm. I doubt it will be used though.

 

[mrmt]

Theoretically A Temash successor could benefit from FD-SOI, provided AMD is stuck with Glo-Fo and would otherwise have to use "vanilla" 28nm. I doubt it will be used though.

AMD is stuck with GLF at least until 2024.

 

[SocketF]

If I had a LP/SLP process that could go head to head with my competitor's HP/HPP on performance and costs, I would go on record and and say exactly this and would invite every HP/HPP possible to make risk production runs with me ASAP, and not just point out how easy is to port to my HP/HPP FDSOI from bulk and mention LP/SLP as my TAM.

Ever heard of the "Not-invented-here" syndrome? They did not even list FD-SOI on their roadmap.

 

[Idontcare]

Ever heard of the "Not-invented-here" syndrome? They did not even list FD-SOI on their roadmap.

We will just have to take a wait-and-see approach to this. I remember when folks got excited over the prospects of AMD using isotopically enriched silicon substrates (silicon-28 to be specific)...only that technology prospect did not pan out in the end.

So far what we have with FD-SOI is a flurry of hype press releases all coming from the one business entity that stands to financially gain the most if it can convince GloFo customers to convince GloFo to pursue ramping it to production.

Obviously STM needs critical mass to accumulate behind FD-SOI if it is to turn into a licensing revenue pot of gold, and critical mass starts with gaining mindshare, hence the PR blitz.

What is telling is how much GloFo is not playing up FD-SOI, to be compared and contrasted to how much GloFo is playing up their existing FinFet roadmap.

GloFo would know, better than anyone outside STM, if FD-SOI is really all that it is hyped to be...and so far, based on what they do know, they are intentionally downplaying the placement of FD-SOI with respect to their bulk 28nm HKMG offerings. That isn't what you'd expect GloFo to do if GloFo thought 28nm FD-SOI offered them any opportunity whatsoever in competing with TSMC and UMC.

STM's PR blitz is as expected, they are trying to get top-dollar for their IP in licensing to GloFo. But GloFo is clearly not as convinced as STM that FD-SOI is all that STM touts it to be, otherwise GloFo would not be so conservative and guarded in their own commentary towards the technology.