What was really unexpected to me, is that it seems that they got a virtual monopoly of 28nm parts. Even when preparing to ramp up 20nm and get a huge customer like Apple, they are still aggressively adding 28nm capacity. And they expect 20nm to take over 28nm only in 2017.
It will be interesting to follow the small boys in the node business, UMC, SMIC, it doesn't seem that they will have an easy time in getting 28nm leftovers, as there isn't any leftovers to get in the first place.
TSMC balance sheet is essentially clean, they financed their current expansion so far with cash flows and cash reserves, but given the new commitments they announced, 9 billion, they should get some debt by the end of the year.
I believe it is still too true this day, but I remember reading some 4 or 5 yrs ago that if you summed up all the profits ever made (as an entire industry) by foundries in the foundry business then you would find that TSMC's financials account for 100% of those profits. That every single other foundry that has ever come (and gone) into existence has only lost money overall trying to be a foundry.
The wild card there is that I don't know if Samsung finally broke that mold, if their recent foundry profits have finally overwhelmed their outstanding losses in the foundry division.
As for the little guys, they all fell behind at the exact same time for the exact same reason IMO. See up through the 65nm node we had a operating environment at TI in which we internally developed our nodes while simultaneously working hand-in-hand with three separate foundries to make sure there was ample capacity around the world for us to "launch with volume" on our mobile products.
This policy started sometime around the 0.18um node. What it meant was that the little guys, UMC, SMIC, Chartered, got to benefit from a behind the scenes push to get their nodes ready in a reasonably timely fashion. We'd intentionally transfer (our) technology to the lagging foundries to help them along when and as needed, TSMC included.
That model disintegrated at 45nm because that was the same node in which TI abandoned internal CMOS development (so we had no 45nm technology of our own to transfer to multiple foundries at will) and eliminated our policy of working with multiple foundries at the same node.
And what you saw with the foundries, all of them including TSMC, at 45nm was everyone took one big stumble. From my perspective it was expected because I knew for years how much TI was subsidizing the foundry world's node-development model. Kinda like welfare, it helped TI but prevented the foundries from every truly developing an independence.
TSMC grew up, so to speak, with 40nm (ergo all their ramp-to-volume teething issues) and are now fully independent for all the right reasons at 28nm (and it shows).
So what are the little guys doing now? Essentially theft, ala industrial espionage. Poaching key employees from TSMC for the purposes of extracting process knowledge. They do the same with vendors, they will buy a vendor's tool and process if the vendor can assure them it is similar to TSMC's BKM (best known method).
Samsung is the other foundry that has been rocking their process development efforts, they will give TSMC a run for its money.
@IDC:
Please correct me, if I got something wrong, or if you know even more meanings of "tape out" :hmm:
Close enough, you got the gist of it.
Technically speaking tape-out was the event in which the tapes were finished and were ready to be shipped to the mask shop (to make the reticles for the litho tools), a step that preceded anything being sent to the fab.
But your point still stands which is that taping out has little to do with process technology readiness. And the reality is so-called "sampling" also has little to do with process technology readiness because sampling just means you throw wafers at an existing mask set and pray you get one or two functioning chips out of the lot (24 wafers).
And it doesn't mean the lifetime reliability aspects are anywhere close to being finished. The two chips you get from the fab might have an expected lifetime of 30 days depending on the health of the node still under development at the time.
Hmm well ... These numbers seem huge, but still I want to know their current desities. All I know is that GF advertised their 28nm gate-first process to save ~20% of die-space compared to TSMC's gate-last. So if both foundries switch to 20nm, it would be only natural, that GF's scaling would be worse.
However, I agree that 1.9x and 1.16x is a rather huge difference. Even if we include the 20% GLast<>GFirst difference, TSMC would still have a big advantage at 20nm. I really wonder if this information is true. Maybe GF's founder would say the same just the other way round?
Yeah you have to be wary of news being brought to you by the competitor.
There is no way GloFo is targeting such poor density increases for 20nm over 28nm unless they are in crisis mode to do something about the growing timeline gap between them and TSMC.
What is more likely is that GloFo will work to deliver entitlement density increases but their 20nm won't be volume-ready until 18months after TSMC, same as 28nm.