electrical engineering requirements

[Net]

I graduated in EE. Everyone here pretty much answered your question. So I'll cover the requirements in terms of getting into the major and how you can speed up the graduation process.

I'm going to assume you are in high school, if you are not please don't be offended.

If you want to get into the program as soon as possible do what you can to have Calculus 1 & 2 completed along with physics of newtonian mechanics and physics of electricty and magnetism. A B average of those and some other classes was the minimum to get into the major at my universtiy. Every university will have different requirements. Check with your university.

If you can get your math and physics prereqs done by transfering high school AP classes you'll save a lot of time.

Some junior college's provide a bridge program where you can take college classes while in high school. The idea is to then transfer those classes to the university you'll be attending. You might be able to take some of the prereq classes mentioned above that way and transfer them to your university. The ability to do that will depend on the junior college and the university that you will be going to.

 

[TecHNooB]

The analog stuff is also about 239048032 times harder then the digital/ programing stuff.

Disagree. The grader makes mistakes. The assembler/compiler are cold blooded and efficient at torturing your soul.

 

[mutz]

I'm going to assume you are in high school

lol, what made you think that?
anyway,
i can see a direction currently.
there are still many interesting things to see and understand that can be obtained over the internet, there's a lot of useful data for whoever searches,
i don't know and really not sure if it can take you to be able to design chips, yet there are many fields still to investigate, before getting into anything serious, it is wise to figure how everything beneath it operates, that gives one, a wider point of view and so more options to play with.

aside from that, there's a nice article on nehalem and interview with 2 of Intel's guys, one is supposed a principal engineer and part of the architecture group on Nehalem, the other is supposed a senior product marketing engineer for desktop processors and they refer to a point raised earlier in this thread:

Q. What were some of the key design challenges Intel faced in transitioning to six cores?

RS. When you scale things to a new manufacturing process, structures scale differently, right? Piecing everything back together so you don’t break some of your key circuits and how things are placed next to each other is hard. I’m not a designer myself, but when I talk with our designers, they talk about how in the good old days, it was so much easier to remember all the process design rules—how close a transistor can be to this or that feature or how structures are positioned. Now the rules are very, very complex. Nobody can memorize them all.

that's Ronak Singhal.
http://www.computerpoweruser.com/ed...=articles%2Farchive/c1005/31c05/31c05.asp
interview at the bottom.

so this is true,
things do get more complicated and complex with technological advancement,
they raise a point that many participants from different aspect of the design are joining together to build a 248mm^2 chip. (lol).
anyway, it just gives you an idea of how complex and demanding such project is, and what makes it a truly magnificent piece.
if you take a look at a processor and you are aware at the huge hurdles that come along the way of those who created it, that makes you really appreciate this work of art,

this is art.

 

[schenley101]

lol, what made you think that?
anyway,
i can see a direction currently.
there are still many interesting things to see and understand that can be obtained over the internet, there's a lot of useful data for whoever searches,
i don't know and really not sure if it can take you to be able to design chips, yet there are many fields still to investigate, before getting into anything serious, it is wise to figure how everything beneath it operates, that gives one, a wider point of view and so more options to play with.

aside from that, there's a nice article on nehalem and interview with 2 of Intel's guys, one is supposed a principal engineer and part of the architecture group on Nehalem, the other is supposed a senior product marketing engineer for desktop processors and they refer to a point raised earlier in this thread:


that's Ronak Singhal.
http://www.computerpoweruser.com/ed...=articles%2Farchive/c1005/31c05/31c05.asp
interview at the bottom.

so this is true,
things do get more complicated and complex with technological advancement,
they raise a point that many participants from different aspect of the design are joining together to build a 248mm^2 chip. (lol).
anyway, it just gives you an idea of how complex and demanding such project is, and what makes it a truly magnificent piece.
if you take a look at a processor and you are aware at the huge hurdles that come along the way of those who created it, that makes you really appreciate this work of art,

this is art.

The way intel designs and lays out a processor is very different than 99% of companies. They still do lots of "by hand optimizations" instead of leaving most of that up to a synthesizer. they can do this because they have enormous resources and many highly specialized engineers and designers. they also are full integrated with manufacturing so they include more of the physics in their design process instead of just foundry guide lines and standard cells.

 

[mutz]

The way intel designs and lays out a processor is very different than 99% of companies.

what do you base that upon? and how many companies designing chips are there?
as far as i know, major chip design is being done by Intel, AMD, IBM, maybe even VIA and late Sunmicrosystem i.e Oracle and Nvidia? yet i don't know much about the difference between designing a CPU and a GPU..., of course there is Matrox too from the GPU aspect at least.

there are also many controller manufacturers yet as far as i know, controllers are much simpler to design than CPU's.
texas instruments, Cytrix E: bought by NS and then VIA which seems to have stopped using it's name, SIS, LSI, ARECA, taiwan semiconductors, Micron, Jmicron etc. etc. etc.

They still do lots of "by hand optimizations" instead of leaving most of that up to a synthesizer.

you talk about HLS?
i highly doubt any big company which is intensively dealing with chip design is basing it's end product totally on HLS tools, i think it's more of a layer placer which does a systematic work, general work which would take much longer to put by hands, more as an assisting tool and less serves as a tool which defines the architecture by implementing algorithms to.

they also are full integrated with manufacturing so they include more of the physics? in their design process instead of just foundry guide lines and standard cells.

this i'm missing..

 

[mutz]

well, any clarification would be appreciated,
we are trying to study here, at least i am.

 

[CountZero]

well, any clarification would be appreciated,
we are trying to study here, at least i am.

What he means by Intel does it different is that there are three different ways to do the actual layout of transistors. One method is to do it all by hand and hand tune it for speed/power as you go. An other method is to make a set of standard logic gates (AND, OR, etc), memory elements and some hand tuned macros (register files) and you use a flow that translates verilog (or another hardware description language) into gates and macros and then use tools to place the gates and route the connections. There is a third way which is sort of a mix of the two maybe you use standard gates but place and route by hand.

From what I have heard Intel uses the first or third of the methods I described for the core and the second method for the uncore portions though I don't know that they have ever really come out and said that, it is just hearsay.

What he was talking about with process design rules is more about feature size. In school we used 180nm which was pretty straight forward, nearly all spacing rules could be expressed in terms of feature size. But as you go down to 90, 60 and 40 the relationship and rules for laying down metal and the other layers to make a chip get more complex and less straightforward.

 

[mutz]

What he means by Intel does it different is that there are three different ways to do the actual layout of transistors. One method is to do it all by hand

by hand meaning instead of using a tool to implement the layout, they use some CAD software to design potions of the chip and create masks of of the sketch?
i'm quite shaky with this.

An other method is to make a set of standard logic gates (AND, OR, etc), memory elements and some hand tuned macros (register files) and you use a flow that translates verilog (or another hardware description language) into gates and macros and then use tools to place the gates and route the connections.

so by hand, is doing everything from scratch (yet i think some potions are anyhow being made by libraries i.e build the bigger from the smaller).
as far as i understand, both ways are needed,
one of the guys here explained it in an earlier thread, that they build smaller blocks of memory to create bigger ones out of them, a 1 bit adder is multiplied to create a 16 bit one etc.

there was a discussion over XtremeSystems where guys were pointing out that AMD's die size is smaller then Intels one and performs almost alike,
they were mostly referring to the X6 series, the 1055T yet i think it is hard to compare a 4 core nehalem (with 4 virtual cores) to a 6 native core chips.
if you take them both by die size, intel's die is ~13% bigger, you can add the HTT to it which AMD lacks, 346mm^2 vs 263 by bloomfield, 57.6^2 mm per die for thuban and 65.75 for bloomfield.
die per die performance if i recall correctly, are about the same or in small favor toward Intel,
so i think the argument of "intel has got more resources so they can do it, is not entirely true", i think, intel do have more resources and background with design, and some other things, yet, basically, the approach of these two companies are quite different and i think it obviously straightly affects they're products.

AMD manages to offer a slightly lower TDP with 6 cores than Intel does with the 920 4 cores and with a higher clock (though it might be the same as intel would sell it's 975 at a mainstream price).
it's very hard digging information from the scatter and reading between the lines in order to find something useful,
yet i think they must be doing something or most of the things, the same, i think they're difference lays from the earlier mentioned point.

What he was talking about with process design rules is more about feature size. In school we used 180nm which was pretty straight forward, nearly all spacing rules could be expressed in terms of feature size. But as you go down to 90, 60 and 40 the relationship and rules for laying down metal and the other layers to make a chip get more complex and less straightforward.

i'm not sure what you are talking about with rules here.

 

[CanOWorms]

by hand meaning instead of using a tool to implement the layout, they use some CAD software to design potions of the chip and create masks of of the sketch?
i'm quite shaky with this.

Yes, they'll use software from Cadence, Synopsys, Mentor Graphics, Magma to design the layout manually.

You can go to Google images and do a search for "ic layout" to see what it looks like. Here's a link I found there: http://pages.cs.wisc.edu/~bsmehta/555/project/layout_ctrlic.png

i'm not sure what you are talking about with rules here.

There are design rules you have to follow when making the layout or physical design. For example, in that link above, there will be requirements on the minimum width of each metal layer, minimum distance between different interconnects, etc.

 

[mutz]

Yes, they'll use software from Cadence, Synopsys, Mentor Graphics, Magma to design the layout manually.

You can go to Google images and do a search for "ic layout" to see what it looks like. Here's a link I found there: http://pages.cs.wisc.edu/~bsmehta/55...out_ctrlic.png

oow, lovely,
there seems to be a lot of information to dig around .

 

[DanDaManJC]

There are design rules you have to follow when making the layout or physical design. For example, in that link above, there will be requirements on the minimum width of each metal layer, minimum distance between different interconnects, etc.

those rules come from simplified physics equations EEs use to model the transistor... for larger manufacturing processes, you have more fudge room and some of the physical limits of the tech don't show up... but as you get into smaller and smaller processes, those simplified equations work less and less well so you need to start making the approximation equations more and more complex.

Thus as an EE working with these tools, you cant work this stuff out by hand at all with paper and pencil... but you'll have to have all this background info in your head. The easier equations provide a good base to start designing this stuff too --and would give you ball park figures when you start designing in ICs.

 

[PsiStar]

As design rules fail there is always the mathematical route but even the simplest problems becomes mathematically intense. Several posts ago I mentioned software from Ansoft & CST. Others have mentioned other software and is correct although it is amazing how quickly specialized some of these can become.

The Ansoft & CST software can analyze electrical performance of complex arbitrary 3D geometry. It is scalable analyzing complex phased array radar antennas measuring several meters across to antennas embedded in the human body .... to electrical circuits with line widths measured in a few microns.

All of this software has its limits. It is after all using models (which are what design rules are). No models are total ... and why they are models!:hmm: And do not take for ever to analyze. Software as this is constantly being updated. Issues as being able to import complex geometry from other sources to improving boundary conditions or material property models are constant challenges. Just measuring the electrical material properties "better" is a constant challenge.

This is just the electrical part of the physics. Bigger companies (as Ansoft & CST) are pushing multi-physics solving capability now. Thermal conductivity & mechanical stress are equal part of the design. NOT to mention statistical analysis .... multivariate vs Monte Carlo ... just HOW accurate does a certain dimension need to be before it is not cost effective? For instance.

The solving. The "solving" process has consumed every termed computer method invented. Maxing 16 cores for the same problem ... not necessarily passe, but it can happen. Distributed computing, yes. A problem might run on many PCs simultaneously. Given the cost of hardware ... no big deal; the software options for this are plenty salty tho. GPU hardware acceleration, yes.

The point is; is that there is something for everyone. There is fun for everyone. Each new invention has to be tested and validated. "invention" might be in software or something tangible that the software has analyzed. The EE "specializing" still has many directions to go ... just try to pick a few that are your interest.

 

[TuxDave]

Yes, they'll use software from Cadence, Synopsys, Mentor Graphics, Magma to design the layout manually.

You can go to Google images and do a search for "ic layout" to see what it looks like. Here's a link I found there: http://pages.cs.wisc.edu/~bsmehta/555/project/layout_ctrlic.png



There are design rules you have to follow when making the layout or physical design. For example, in that link above, there will be requirements on the minimum width of each metal layer, minimum distance between different interconnects, etc.

No no... we use very tiny chopsticks to put the transistors where we want them. If it was as easy as using software, why would we be paid the big bucks that we do?

>_> <_<

 

[mutz]

hm,
was wondering, what do you think about it:
http://spectrum.ieee.org/nanoclast/...tionless-transistor-fabricated-from-nanowires

what does it mean for an end product?
and what are your thoughts :hmm:.

 

[esun]

The trick with all of these new transistor designs is always how to put a billion of them on a chip with a reasonable yield and without substantially changing the process.

They claim in the paper that their technology integrates with a standard CMOS process, but I'd be skeptical until we see more than a couple transistors fabricated. Also note that from their images it looks like the transistors were fabricated with a channel length of around 30 nm, which we know we can do with conventional CMOS technology (though performance differences might be interesting to look at). Demonstration that it is feasible at sub-10 nm would be far more interesting.

There is a lot of research going in to what will replace conventional CMOS technology once we get in the sub-10 nm range. If you're interested in the contenders I'd recommend reading the relevant sections of the ITRS.

 

[mutz]

o.k, that should be enough matter to go through the next few months,
thank you for your input, everyone :thumbsup:.

 

[mutz]

o.k, few things to add as an epilogue,
1st,
as for the story about the guy who didn't want to dig into the Japan internet infrastructure,
the story was about the designing of microprocessors,
the question was asked later on at this forum, and got answered, as much as guys here could,
the story on the japan network, was lent to another guy at about the same period, and got clearer,
this wasn't the case, so this should void any confusion.

as for processors or technology getting more complicated,
well, they seem to go that way,
there is no way they could've designed chips they do today, few years back, technology grows, and as it grows, so designers and the design itself,
the architects understanding of the logic is getting vaster and better, and so more complex structures can be made.
this is natural and understandable, and there wasn't any need to bring Intel's employees quote for it.
they get better with hard drives, SSD's, controllers, heck, even FPU's weren't inside earlier CPU's once, we can see it happening, operating systems are much more complex to design and understand currently, windows is much more complex then dos, there are much more lines of code, yet in a way, maybe they do get simple with time,
from the pov that everyone can use them, data is available,
i think they get both,
simpler and complicated.
the only thing that is for sure ,
they get much more prettier .

 

[bommy261]

and also, you end up learning all that math so you don't have to use it. thank goodness for Laplace and Fourier.

you learn all that stuff so you become better at learning. if you can initially grasp fourier and understand signal processing, programming a PLC for example is not that bad.

 

[mutz]

you learn all that stuff so you become better at learning. if you can initially grasp fourier and understand signal processing, programming a PLC for example is not that bad.

that is so true,
when getting stuck on some hard material, learning even tougher one makes the earlier instantly, much easier.

 

[PsiStar]

In one of my early engineering classes, the math & higher level math was justified to help the student to better define a problem (in general). If you do not have a definition of the problem, then you do not know what to solve for a solution. This is about logic, learning what it is, & how to apply.

As far as the concepts of transforms to tensor algebra (ha!), after 30 years, I use them almost daily as I am a consultant! Fortunately I have long ago been able to put aside the actual math with pencil & paper ... do not even need anything like MathCAD (although I have it), but it is very helpful to the understanding of the underlying methods in the electromagnetic modeling software I use.

The dominant intellectual content of engineering problem solving, the business of modeling, is at bottom pure logic ... geez, now I feel I should have made a poll of "profound statements of the day", but I don't have time.Actually, I am thinking about a glass of red wine at the moment ... for health reasons of course. Ok, I really do think I have a "life".:\