PC Polaris has less features than PS4 Polaris, and at the same time, AMD delayed Vega after PS4 PRO launch.
Show me the error in my reasoning. (Saying its a custom APU its not valid, neither is to blame it on DX11/12)
AMD didn't screw over anyone, this is an absurd statement.
Primarily because a graphics card is advertised to perform a certain way at a certain price. That deal didn't change. And can you provide any proof Vega was delayed? You actually think AMD would purposely delay it's next major Graphics chip for 2% of consumers "perceived" value in PS4 PRO?PC Polaris has less features than PS4 Polaris, and at the same time, AMD delayed Vega after PS4 PRO launch.
Show me the error in my reasoning. (Saying its a custom APU its not valid, neither is to blame it on DX11/12)
PC Polaris has less features than PS4 Polaris, and at the same time, AMD delayed Vega after PS4 PRO launch.
Show me the error in my reasoning. (Saying its a custom APU its not valid, neither is to blame it on DX11/12)
The ID buffer seems like it could be a game changer. A pretty obvious innovation in hindsight.
The extra 1GB of DDR3 was a bit of a surprise as well, but does a good job of explaining why the Pro has more usable memory for games.
This GPU is going to be able to hit way above its weight class. Certainly above a 480 despite a modest deficit in raw numbers. Console devs will make use of FP16 everywhere they can get away with it given time. If Vega has the ID buffer as well, I could see it besting the new Titan given proper software support. Of course, I imagine most rendering techniques would be incompatible with other GPUs, making any comparison necessarily apples-to-oranges.
So AMD screwed us, the PC gamers, by selling an inferior product than they sold to consoles AND delaying superior products than consoles, thank you again, and thank you all who recomended to buy an RX480 because its the same gpu used on the PS4 PRO, its not either.
Vega and what has been discussed gives at least hope that this will be first true next generation GPU from any of the Vendors(Polaris is just slightly tuned Tonga on 14 nm process, and Pascal is slightly tuned Maxwell on 16 nm process). If I have to use analogy, Vega in change of architectures will be like Maxwell was for Kepler, or Pascal GP100 for Maxwell. Tuned, but much different.
Awesome write-up by Digital Foundry and great level of detail by Cerny. Unlike MS that wants to abandon console generations, Cerny outright hints he wants a PS5 as a clean slate design, even fin it means breaking BC with PS4/Pro. I am looking forward to that. I hope we see PS5 with 7-8Tflops by 2020 at the latest, preferably by Fall 2019. Given how great The Order 1886, Uncharted 4, Driveclub, InFamous First Light look on a 1.8Tflop PS4, I am pretty exited for PS5 by the end of this decade. Horizon Zero Dawn looks incredible when looking at rather mediocre low-end specs of PS4. I am not particularly excited about PS4 Pro since Sony will not allow any exclusives. Seems like a nice mid-cycle $399 console for those who haven't purchased the original PS4 yet. Still, the prospects of a 2019-2020 PS5 with 6-8 core Zen, Navi+ era GPU with 16GB of HBM2 would provide for a great generational leap.
Well if you define new architecture by how much it gains clock for clock from previous generations then yes, Pascal consumer cards are not new architecture, but GP100 - is.Pure nonsense. I've been hearding this for every uarch since Kepler came out. The supposition being that Fermi was the last "real" uarch and rest are minor tweaks with new nodes. The same BS has been made (invariably by the same cast of people) with regards to AMD.
If you don't understand something, just claim the current GPU is a tweak of an older GPU with a new node. Old trick but seemingly never goes out of fashion for the ignorant. Spend some time at B3D and educate yourself.
One GCN CU can have up to 40 waves running concurrently (10 per SIMD). It doesn't matter where each wave has originated. There can be any mix of pixel/vertex/geometry/hull/domain/compute shader waves in flight at the same time (from any amount of queues). Instructions from these 40 waves are scheduled to the CU SIMDs in a round robin manner. If some of these 40 waves is waiting for memory, the GPU simply jumps over it in the round robin scheduling.
There is no need to store wave's data in off-chip memory. Each CU has enough on-chip storage for the metadata of these waves. Waves are grouped as thread groups. A single thread group needs to execute on a single CU (this is true for all GPUs, including Intel and Nvidia). This is because threads in the same thread group can use barrier synchronization and share data through LDS (64 KB on-chip buffer on each CU). All GPU architectures use static register allocation. The maximum count of registers used during a shader life time (even if some branch was never taken) needs to be allocated for the wave. Simplified: The GPU scheduler keeps track of available resources (free registers, free LDS, free waves) on each CU. When there's enough registers on some CU for a new thread group (thread group = 1 to 16 waves), the scheduler spawns a thread group for that CU. Each GCN CU has 256 KB of registers, 40 wave slots and 64 KB of LDS. There is no need to context swap kernels (*). Each thread group is guaranteed to finish execution once started. GPU programming model doesn't support thread groups waiting for other thread groups (atomics are supported, but the programmer is not allowed to write spinning locks). Nvidia GPUs work similarly. Intel has per wave (they call them threads) register files. Their register allocation works completely differently (shader compiler outputs different SIMD widths based on register count).
(*) Exceptional cases might need context switch (= store GPU state to memory and restore later). Normal flow of execution doesn't.
16 waves * 64 threads/wave = 1024 threads. That's the biggest thread group size supported (required) by DirectX. 64 KB register file / 1024 threads = 64 registers/thread. If you need more than 64 registers per thread, the compiler is going to spill to memory (or LDS). A CU can run two 1024 thread (16 wave) thread groups at the same time, if your shader needs 32 or less VGPRs.
The image printed on wall of every console graphics programmer:
1024 threads (16 waves) is not an optimal thread group size for GCN. It doesn't evenly divide the 2560 thread CU maximum concurrent thread count (40 waves). 1024 thread group cannot achieve max occupancy (max latency hiding).
Good GCN thread group sizes (max occupancy): 64, 128, 256, 320, 512, 640.
But maximum occupancy is only achievable in shaders with no more than 256 KB / (2560 threads * 4 bytes/register) = 25 registers/thread.
Sometimes larger thread groups (than 640) are the best choice, as it allows sharing data between larger groups of threads. Max occupancy is not always equal to best performance.
Heterogeneous loads are a big performance win in many cases on GCN. There are many real world examples available (look at recent GDC/SIGGRAPH presentations).
Common examples are:
- One kernel is sampler bound and the other isn't. Example: parallax mapping (N trilinear/aniso taps for root finding), anisotropic filtering in general (multiple textures), bicubic kernels (3x3 bilinear taps per pixel), blur filters (N bilinear taps), etc. A pure compute task (no tex filter instructions) can fill the execution gaps nicely.
- One kernel uses lots of LDS (thread group shared memory) and this limits occupation. Other kernel with no LDS usage increases occupancy.
- One kernel is heavily memory (and L1 cache) bound, while the other is mostly math crunching (ALU instructions using registers and/or LDS).
- Tail of another kernel. Work finishes at wave granularity (after last barrier). Waiting for the last wave to finish means that processing cycles are lost on each CU (every time kernel changes).
- Resource bottlenecks (waves/registers/LDS). Kernel allocates some CU resources heavily, while other resources are left unused. It is better to schedule thread groups from multiple kernels (different shader) to utilize the CU resources better.
- Uneven split of resources. There are cases where a single kernel doesn't evenly divide all CU resources (waves/registers/LDS) between thread groups (see my post above). Reminder is left unused. Better to schedule multiple kernels (with different resource counts) to use all the resources.
The most common heterogeneous task is executing vertex and pixel shader on the same CU. Vertex + hull + domain shader is another example. GCN is not limited to running multiple compute shaders concurrently on the same CU. You can have a mix of different graphics kernels and compute kernels.
Sebbbi was lead console engine programmer at Ubisoft (one of their engines,don't know which one).He is now lead for Unigine next gen.He definitively knows his stuff.That beyond3d member sebbbi sure knows his stuff. Very interesting to read his(hers ?) posts.
Sebbbi was lead console engine programmer at Ubisoft (one of their engines,don't know which one).He is now lead for Unigine next gen.He definitively knows his stuff.
Also,when laymen like us can understand complex stuff he is talking about,that is straightforward sign that he really knows what he is talking about.
Yeah,I meant Unity.Yeah, he was the lead graphics programmer at redlynx(the guys who make trials). In fact, the latest engine that he worked on before he left still hasn't been deployed in any released game yet. Still very excited to see what it can do.
But he's actually indie now, and co founded his own company. So, not unigine(or unity if that's what you meant).
PC Polaris has less features than PS4 Polaris, and at the same time, AMD delayed Vega after PS4 PRO launch.
Show me the error in my reasoning. (Saying its a custom APU its not valid, neither is to blame it on DX11/12)
Unfortunately, this is the same architecture as Maxwell, with few tweaks. And remember, Maxwell was supposed to be 20nm arch. first, but because of the fail of the process it had to be ported back to 28 nm, with excluding of some of the features from the uarch.
It's more reasonable to call Pascal Maxwell+ since it's theoretically better at handling DX12/Async compute. The fact that NV introduced dynamic scheduling into Pascal shows that if they were to scale their CUDA cores, they may also run into shader under-utilization as GCN has. It's probably why NV is building the ability to perform more parallel concurrency into their future GPU architectures since they know DX12 is the future and DX11 serial workloads will be outdated at some point. It seems logical that the more shaders there are, the more chance of shader underutilization
Sony requires certain things that RX 480 users will never care for -- like 4K checkered upscaling.
4K checkered upscaling isn't a hardware feature per se. The hardware feature is the ID buffer, which enables techniques like Sony's checkerboard rendering. And the ID buffer is definitely something I'd love to see in PC graphics, since it opens up many possibilities in addition to upscaling. Eventually I'm sure the feature will become ubiquitous, but in the meantime AMD could use it to give Nvidia a taste of their own medicine - eg. vendor locked settings.
I don't think the id buffer is required for checkerboard really. It just improves the effectiveness.
Also, I believe Nvidia might already be using id buffers as well.
It's required, unless you were to replicate the ID buffer in software, which isn't practical. You can't just do it "less quickly" because the algorithm requires information from the ID buffer to function. You either have the information and you can apply the technique, or you don't and you can't. There's no in between.
If Nvidia has it, it would already (or will very soon) be used in proprietary middle ware. "Temporal AA-Works" and such. Why else would they build in such a feature? It might be an outside chance that something about Nvidia's architecture lets them emulate an ID buffer at some more or less reasonable performance cost, though that's beyond my knowledge.
Well, I don't know for sure. Rainbow Six used a custom chaeckerboard implementation. No idea if they used an ID buffer or not.
I think someone said it was required for tiled rasterization. Probably on B3D somewhere.
Don't remember exactly, might've been something else.
I'm assuming not, unless they did so in software which seems unlikely.
Ubisoft did implement checkerboard techniques in Rainbow Six: Siege. Page 48
Frame reconstruction in a checker board pattern is about as broad a description as post process anti aliasing. Eg. a lot of ways you can go about it. Another example, temporal AA has been around forever, but better detection of mesh edges via the ID buffer enables higher fidelity implementations.
I'm assuming not, unless they did so in software which seems unlikely...Another example, temporal AA has been around forever, but better detection of mesh edges via the ID buffer enables higher fidelity implementations.