If Fermi will really take as long as May or later to launch, AMD's 5xxx series is almost sure to be a lot more widespread. That makes for atleast half a year of only the 5xxx being the latest and greatest.
IDC, are you saying millions of dollars of wafers are now useless, also implying that they ended up wasting several million dollars?
Well first we don't know they actually staged 9000 wafers with A1 steppings already used for the FEOL layout...that was simply rumors that had been so prevalent that both myself as well as Charlie appeared to have been fed very similar infos. Could be we were all fed the same info from a common source of misinformation.
I was just thinking out loud that
if the 9000 wafer banking rumor was true and
if the A3 silicon respin rumor is true
then there is very very low probability that the banked wafers will still be usable at this stage in the game and they would most likely be scrapped.
Now along with the same rumorings of a 9000 wafer banking plan was a rumor that the contractual obligations for payment of those wafers were strongly correlated to yield. If yields are in the dumper then TSMC would not have been paid for the wafers anyways regardless whether they had parametrically functional IC's on them or not.
So
if all these rumors were/are true and the ramifications play out as I'd imagine them to then it still doesn't answer the question as to who eats the cost of scrapping those 9000 wafers.
I always wondered, would parking wafers like that decrease the number of usable chips you get out of them in the end?
It inevitably increases the functional yield losses as there is no way to absolutley eliminate fall-on defects that accumulate over time. There are protocols in place of course to attempt to remove as many of them as possible when the silicon is introduced back into the line, but nothing is 100%.
Aging material in the fab also gives rise to another difficult to avoid phenomenon referred to as "resist poisoning" in the industry. The more time you give the material on the wafer to diffuse thru the various layers in the wafer, even with meager room-temperature thermal budgets driving the diffusion, the less margin the photo guys will have at the next patterning step when the silicon is brought out of bank and restarted. Again there are things done to pro-actively mitigate these effects, including the decision of where in the process flow the wafers are to be parked, but just like putting bread in the fridge instead of leaving it on the counter only delays the inevitable molding of the bread so too are the issues of inevitable time-window effects on the process integrity for future steps that are going to be used on the chips.
It's a calculated risk, obviously it would never be done if it turned out to never give anyone a benefit by doing it.