First Steamroller processor core exposure

[d3m]

 

[Erenhardt]

Rather than be cautious about their wishful thinking clouding their judgement, they double down on their silliness and predict that Bulldozer would be the fastest desktop processor.

If you consider Piledriver as a revision of Bulldozer, then FX-9590 is the fastest desktop x86 processor in a way (5GHz).

 

[Abwx]

There has a first Kaveri ES been reported by a BOINC client (as usual ):

http://citavia.blog.de/2013/07/02/amd-kaveri-engineering-sample-sighted-in-the-wild-16196102/

The original account has been created in March. I didn't see yet, when the computer has been added.

Picture says 2MB cache , that s half of Trinity for the same core amount.

At first glance the scores looks like it s 1.8Ghz with a single
module running two integer threads and a single FP thread.

 

[galego]

Well the die is definitely around 238-240mm^2 as now we have a nice picture with a ruler next to it. We also are not sure if it's GF or TSMC who produces these chips.

Most of their APUs and CPUs are still fabbed at GF
and they re WSA bound so they have no choice
than staying with them , hope the process will
retain the SOI waffers.

I'm not so sure it's GF. With all the delays and low yield reports I wouldn't be surprised if it was somehow made by TSMC.

One of the links given above claims that kaveri is going bulk on GF.

P.S: I find fascinating that the same people who is accusing AMD, without any proof, defend Intel in proven cases of malpractices.

 

[galego]

Some people are just incapable of learning from their mistakes.

Rather than be cautious about their wishful thinking clouding their judgement, they double down on their silliness and predict that Bulldozer would be the fastest desktop processor.

In general bulldozer was not a good step. However, I still can give some benchmarks where the bulldozer 8150 is faster than Ivy Bridge 3770k

 

[Haserath]

So in Bulldozer, the decode had to switch between the cores every cycle, correct?

Couldn't they have made the decode dispatch the more required macro ops to the cores? Like 2/2 or 1/3?

So instead of making 8 decoders per module, they could've done 6 with better sharing?

 

[Haserath]

Some people are just incapable of learning from their mistakes.

Rather than be cautious about their wishful thinking clouding their judgement, they double down on their silliness and predict that Bulldozer would be the fastest desktop processor.

There were many of us that believed Bulldozer was going to be a high clocking ~PII performance 4M chip for the desktop. Doesn't sound unreasonable, right? Would've been a good performer next to mainstream SB; losing in single thread, but making it up on multi.

It's too bad it became worse than the Phenom launch...

 

[mrmt]

It's one thing to predict and be wrong, it's other to be a intel shill/fanboy who derails AMD threads, personally attacks/insults users who disagree, accuse others for things he does himself and all that with no repercussions. Sorry but this happens only here and nowhere else. That's why it's funny and sad at the same time.

How do you call your Terrace IPC decrease procedure?

 

[Abwx]

So in Bulldozer, the decode had to switch between the cores every cycle, correct?

Couldn't they have made the decode dispatch the more required macro ops to the cores? Like 2/2 or 1/3?

So instead of making 8 decoders per module, they could've done 6 with better sharing?

Beefing the modules was on the plan from day one ,
it s just that it s inherently tied to processes shrinks ,
so they couldnt put more decode and exe ressources
for 32nm than that was done in BD/PD.

 

[Haserath]

Beefing the modules was on the plan from day one ,
it s just that it s inherently tied to processes shrinks ,
so they couldnt put more decode and exe ressources
for 32nm than that was done in BD/PD.

That's not what I meant.

I'm wondering whether they could share the decode stage better between the cores.

 

[Abwx]

Decoder isnt wide enough for 2 cores since it can issue
only 4 instructions/cycle but widening it to 6 issues
is surely more complexe than simply duplicating the 4 issues
wide existent hardware , not counting all the spared work.

 

[Haserath]

Decoder isnt wide enough for 2 cores since it can issue
only 4 instructions/cycle but widening it to 6 issues
is surely more complexe than simply duplicating the 4 issues
wide existent hardware , not counting all the spared work.

I thought AMD used the same decoder and duplicated it 3 times, unlike Intel.

But I could see how managing the traffic could be more complex. They need to find ways to improve perf/watt though...

 

[CHADBOGA]

In general bulldozer was not a good step. However, I still can give some benchmarks where the bulldozer 8150 is faster than Ivy Bridge 3770k

Obviously you won't be getting your benchmarks from here.

 

[Abwx]

Obviously you won't be getting your benchmarks from here.

Out of 59 tests 12 are Sysmark , roughly 20% of the total...

 

[Haserath]

Why are we still arguing over the crap that is Bulldozer. If it was given the same power envelope as Ivy, or even Sandy!, it would be a slug.

 

[SiliconWars]

Why are we still arguing over the crap that is Bulldozer.

Maybe you should ask yourself that question first seeing as you're one of the reasons why?

If it was given the same power envelope as Ivy, or even Sandy!, it would be a slug.

Oh so you do actually want to argue more about Bulldozer?

 

[CHADBOGA]

Out of 59 tests 12 are Sysmark , roughly 20% of the total...

Well highlight Bulldozer's glory from the 80% of non-Sysmark benchmarks then.

 

[galego]

Obviously you won't be getting your benchmarks from here.

Obviously.

 

[guskline]

Back on point about steamroller, is there any more news whether or not it will be made for socket AM3+?

No doubt SR cores will appear in socket FM2+ but AM3+???

 

[0___________0]

Back on point about steamroller, is there any more news whether or not it will be made for socket AM3+?

No doubt SR cores will appear in socket FM2+ but AM3+???

Back in 2012 the enquirer claimed that when AMD demoed Vishera for them before release that there would be at least one more chip after Vishera on AM3+ and that all CPU's for a couple years would remain compatible.

Wikipedia lists another source for the AM3+ claim, it's a bunch of PDF's, I don't know if there's actually anything definitive in them though.

 

[grimpr]

Back in 2012 the enquirer claimed that when AMD demoed Vishera for them before release that there would be at least one more chip after Vishera on AM3+ and that all CPU's for a couple years would remain compatible.

Wikipedia lists another source for the AM3+ claim, it's a bunch of PDF's, I don't know if there's actually anything definitive in them though.

I'd say thats a big unknown as of now, the more we approach Kaveris release the more things clear out, i'd love another cpu upgrade from Vishera to Steamroller for my am3+ rig but i keep my hopes cooled down.

 

[AtenRa]

I will say it again, I dont believe SR will be AM3+ compatiple. Next and probable last AM3+ CPU will be PD2 (Warsaw ??)

 

[Idontcare]

I will say it again, I dont believe SR will be AM3+ compatiple. Next and probable last AM3+ CPU will be PD2 (Warsaw ??)

SR is "APU only", right? No discrete CPU SKUs IIRC.

 

[Tuna-Fish]

So in Bulldozer, the decode had to switch between the cores every cycle, correct?

Couldn't they have made the decode dispatch the more required macro ops to the cores? Like 2/2 or 1/3?

So instead of making 8 decoders per module, they could've done 6 with better sharing?

In a word, no. For x86, adding more decoders gets exponentially more expensive for each decoder. Both in transistors and decode time. The fundamental problem is that x86 instructions can be of any length between 1 and 15 bytes, and to decode you need to find instruction boundaries and match decoders to them. Increasing decode by just one might well have taken more area than duplicating units and giving one for both threads. Also, if I understood it correctly, SR decoders are only 3 wide, which should have made them much smaller and cheaper.

Also, since the decode is really a single unit where most of it's work is finding instruction boundaries, it can't feasibly work on both threads at once. So no single-cycle sharing.

IMHO moving towards split decode makes sense. That part of BD never made sense to me -- they took the part of the chip that's ridiculously expensive to beef up, beefed it up and shared it. The only way the BD decoder made sense was if there was going to be a trace/uop cache of some kind after it. There wasn't.

 

[NTMBK]

It's one thing to predict and be wrong, it's other to be a intel shill/fanboy who derails AMD threads, personally attacks/insults users who disagree, accuse others for things he does himself and all that with no repercussions. Sorry but this happens only here and nowhere else. That's why it's funny and sad at the same time.

edit:
This is one example how SR topic became "AMD shill/fanboy topic". People who came here to read about SR core will find very little on-topic information I'm afraid and we know why is that. Paranoia is strange illness.

edit #2:
Nice ninja edit Sweeper (in order to seem you are on topic at least a little bit ), it's been already posted btw.

Sorry for one last off-topic post, but- SHILL != FANBOY.

Calling someone a shill is accusing them of being intentionally deceitful, and being on the payroll of the company that they are shilling for. Accusing someone of being a shill is an excellent way to completely derail a topic, invalidate any points that they may have made, and make people doubtful of anything they ever post in the future. Don't go around accusing people of shilling without some hard evidence, people.