I think AM3+ is pretty much dead. Steamroller looks to be FM2+ only. With the launch of those 220W TDP Vishera's I even have doubts we will see improved Pile Driver (2014 Server roadmap) on AM3+.
SR is "APU only", right? No discrete CPU SKUs IIRC.
I think AM3+ is pretty much dead. Steamroller looks to be FM2+ only. With the launch of those 220W TDP Vishera's I even have doubts we will see improved Pile Driver (2014 Server roadmap) on AM3+.
SR is "APU only", right? No discrete CPU SKUs IIRC.
Steamroller Mainstream/Consumer -> FM2+/FM3
Steamroller Server/Enthusiast -> G34+/GC34/GC36
Excavator Mainstream/Consumer -> H2015/(Socket HM1)
Excavator Server/Enthusiast -> GC34/GC36
The usual rumor mills WCCFTech, DonanımHaber, Blogspot, etc. :sneaky:Do you have a source for that?
You, or those, must be equipped with inconceivably powerful precognitive capabilities.:hmm:The usual rumor mills WCCFTech, DonanımHaber, Blogspot, etc. :sneaky:
Bulldozer/Piledriver Front-ends -> Vertical Multithreading(Fine-grain)
Steamroller/Excavator Front-ends -> Simultaneous multithreading(CMP-like)
Bulldozer/Piledriver FPU Front-end -> Vertical Multithreading(Coarse-grain)
Steamroller/Excavator FPU Front-ends -> Simultaneous multithreading(CMP-like)
5) Will the secretly planned alien invasion have begun by that point of time, and if so, will they buy excavator APUs? And what's their marketshare?
You, or those, must be equipped with inconceivably powerful precognitive capabilities.:hmm:
Just a few more questions before sb. from WTFtech, Dona, etc. tells my fortune:
1) Are you/they sure about those threads per module for SR & ExC?
2) Which architecture does that mysterious die-shot belong to?
3) Who is to say the socket/platform situation is not going to change dramatically with DDR4? Wouldn't it be rational for the company to scrap some of those server platforms altogether and unify them for DDR4 and APU use?
4) Will AMD still be among us by the time Excavator is scheduled to come out?
...
Steamroller/Excavator:
Front-end(2 threads)
2 cores(2 threads)
FPU F-E(2 threads)
2 execution units(2 threads)
Obviously, you didn't read what I posted.yadda yadda yadda
The die shot is Steamroller, it was shown at a convention.And none of that means anything if the die shot is not actually Steamroller.
Which convention?The die shot is Steamroller, it was shown at a convention.
The schematics posted on the previous page would about answer that.So every part of the bulldozer module executes two threads but doesn't employ SMT. In other words it's two completely independent cores, except for L2 cache.
Wait, that doesn't sound right.
Which convention?
Which convention?
^-- assuming it is this one. There are a couple more like this discussing both Steamroller and Jaguar.Tuesday, June 4: 10:30am - 12:00pm
2.1 Physical Design Methodologies on AMD’s CPU Cores
This presentation will cover the physical design methodologies and CAD flows used on AMD’s low-power (Jaguar) and high-performance (Steamroller) CPU cores. Both CPU cores used a wide variety of construction techniques including full-custom macros, custom-placed blocks and synthesis/P&R. Each of these methodologies along with corresponding tool flows will be discussed. We will also give an overview of the tools and methodologies used for static timing, IR, electro-migration, power consumption analysis, leakage recovery and clock/voltage domain crossing. The presentation will highlight some of the unique tool flows developed around in-house and industry-standard CAD tools.
Branch Prediction Thread domain = SMT
The schematics posted on the previous page would about answer that.
http://cdn3.wccftech.com/wp-content/uploads/2013/07/AMD-Steamroller-vs-Bulldozer.jpg
I assume it's not the convention of WCCFTech, DonanımHaber, Blogspot, and etc.
That is because it is.I would note that the diagram looks suspiciously like the diagrams that Hiroshige Goto makes on pc.watch.co.jp.
I lied. I don't provide sources unless I have the PDFs or PPTs on my computer.I assume it's not the convention of WCCFTech, DonanımHaber, Blogspot, and etc.
I lied. I don't provide sources unless I have the PDFs or PPTs on my computer.
Not really. I would prefer you wait and see rather than completely agree with me.care to share then?
Berlin APU for now.PCIe integrated into CPU for direct link to GPU
GPU access to x86 memory
Enhanced server-class RAS
OpenCL driver enhancements
Greater unification:
Server Fusion Architecture: Integration of CPU, GPU and communications with shared memory model
- DMA memory and cache access w/ accelerators
Dynamic load balancing
The issue with this rumor was that it for for 28-nm GloFo not 32-nm GloFo.Transition to TSMC
including those testing transaction processing => TSXDesign to tune up integer execution
bandwidth:
In concert with feeding the core faster
More register resources, same latency
More intelligent scheduling
Design to decrease average load latency:
Minimum latency is only part of story
Faster handling of data cache misses
Accelerate store-to-load forwarding
No compromises two thread performance
Increase instruction cache size(I-Cache Misses Reduced by 30%)
Enhance instruction pre-fetch
Mispredicted Branches Reduced by 20%
Fetching and decoding logic is different from previous fam15 processors. Fetching is done every two cycles rather than every cycle and two decode units are available. The decode units therefore decode four instructions in two cycles.
Not really. I would prefer you wait and see rather than completely agree with me.
i always thought it looks too real to be fake so to speak. enough the same, enough different. But i still dont know what the die shot is. I was hoping if you had a PDF from a presentation or something with the die in it i could see for myself.
without that i am unwilling to assume it is SR at this stage, its to different from hotcips last year. that said given the general size of the core to the size of the L2 im guessing its a 28nm design not 20nm.
Hasn't AMD in the last few years admitted to putting out a photoshopped die shot to throw off Intel?
This could be the same thing again.