First Steamroller processor core exposure

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Vesku

Diamond Member
Aug 25, 2005
3,743
28
86
SR doesnt double the FPUs.

Was referring to the die shot hence "questionable aspect of the die shot". Doubling up was in direct reference to my link where the Hot Chips showed a continuation of the 2x128 bit FPUs but the die shot that started this thread looks to have 4. Everything else about the die shot doesn't contradict Hot Chips 2012 information.
 
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Vesku

Diamond Member
Aug 25, 2005
3,743
28
86
I don't know if they are fake, only that they don't fit with Hot Chips 2012 info. You're welcome to point out signs of editing between the FPUs and the uncore portion on the right.

With GF 28nm so long in arriving (still not here yet) it's not out of the question for Steamroller to be a bit different from projections from a year+ previous.
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,688
1,222
136
October 2012:
128kB 4-way associativity
16kB+16kB Fetches
Two Dbl Macro-op decoders
1,1,1,1 + 1,1,1,1 or 2,1,1 + 2,1,1
So we have no reason to listen to you?
No, I said not to be a religious fanatic. What I say is 90% certain to happen.
SR doesnt double the FPUs.
It does, look again particularly at the arrows that point to the FPU.
 
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Tuna-Fish

Golden Member
Mar 4, 2011
1,420
1,749
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Floating Point Execution Unit 1 = Single Thread
Floating Point Execution Unit 2 = Single Thread

That's not what the diagram says. The FPU execution units are clearly SMT.

It does, look again particularly at the arrows that point to the FPU.

Huh? The two arrows that designate instruction dispatch into a single shared floating point frontend, from which there is a single arrow to a box clearly labeled as "floating point SMT".
 

Abwx

Lifer
Apr 2, 2011
11,166
3,862
136
Expect SR to be released at the time of APU13 in November.

Joining AMD speakers Lisa Su, senior vice president and general manager, global business units; Mark Papermaster, senior vice president and chief technology officer; and Phil Rogers, corporate fellow, are thought leaders from some of today’s foremost technology companies including:

  • Mike Muller, chief technology officer at ARM;
  • Johann Anderson, chief architect at Electronic Arts DICE;
  • Tony King-Smith, vice president of Marketing at Imagination;
  • Chienping Lu, senior director of Mediatek USA;
  • Nandini Ramani, vice president of development at Oracle Solutions;
  • David Helgason, founder and CEO of Unity Technologies;
APU13 will feature breakout sessions focused on industry trends in computing. In February, AMD announced two new additions to the conference agenda including a much-requested gaming focus: the 2013 AMD Game Developer Summit. This addition will showcase the latest GPU and APU technologies and their inclusion in the most widespread or next-generation gaming platforms across mobile, tablet, PC, online/cloud and console.

http://www.xbitlabs.com/news/other/...vators_to_Talk_at_AMD_s_APU13_Conference.html
 

podspi

Golden Member
Jan 11, 2011
1,982
102
106
Yea, I don't think it makes sense of them to roll a new server die just to remove the GPU.
 

Ajay

Lifer
Jan 8, 2001
16,094
8,104
136

I thought EX (or XV as I've seen on some LinkedIn profiles) was supposed to be more heavily synthesized? I haven't seen allot of synthesized layouts, but they do look a bit weird placement wise compared to hand layouts, IMO. But I'm not expert.

I do agree with IDC, the proof will really be in official statement close to launch and actual benches. My biggest concern is that the long rumored lower clocks will turn out to be true. One would hope that AMD would have a couple of SKUs in the 3.0-3.5 GHz range even if it were mainly for show.
 

Abwx

Lifer
Apr 2, 2011
11,166
3,862
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My biggest concern is that the long rumored lower clocks will turn out to be true. One would hope that AMD would have a couple of SKUs in the 3.0-3.5 GHz range even if it were mainly for show.

Thouses rumours are built upon irrational logic.

What would be the purpose of a 100W 3.5ghz chip that
would have 20% higher perf/mhz but 0% delta in perf/watt.

AMD has clearly stated that high frequencies will be maintained
and that perf/watt would be improved.
 

SiliconWars

Platinum Member
Dec 29, 2012
2,346
0
0
Thouses rumours are built upon irrational logic.

What would be the purpose of a 100W 3.5ghz chip that
would have 20% higher perf/mhz but 0% delta in perf/watt.

AMD has clearly stated that high frequencies will be maintained
and that perf/watt would be improved.

You have to consider the overall change to bulk from SOI might have a negative impact as well, if only initially. If things have changed AMD isn't going to go back and revise their slides. Nobody ever does.

I'm not sure why but I'm getting more of a Bulldozer feeling than a Piledriver one about Steamroller. There could be too many big changes there that takes longer to fix that the initial plan was. Obviously I hope I'm wrong.
 

Abwx

Lifer
Apr 2, 2011
11,166
3,862
136
You have to consider the overall change to bulk from SOI might have a negative impact as well, if only initially. If things have changed AMD isn't going to go back and revise their slides. Nobody ever does.

I'm not sure why but I'm getting more of a Bulldozer feeling than a Piledriver one about Steamroller. There could be too many big changes there that takes longer to fix that the initial plan was. Obviously I hope I'm wrong.

SR slides dates from Hot Chips 2012 august while bulk rumours
were already months old at the time of this event...

They officialy aknowledged 100W 2M4C SR , granted the 3.5ghz
limitation is true then a 100W 4C SR would perform the same as a
100W piledriver 4C , seriously , why bother making a CPU that
would be not more power efficient , with all the hassle of a new node..?...

Truth is that viral marketing has big influence to the point
that even sane people start doing theories based on thoses
sensless assumptions.

Monday, June 18th 2012

According to AMD senior VP and CTO Mark Papermaster, the company will adopt the 28 nanometer bulk CMOS silicon fabrication process for its chips in 2013
http://www.techpowerup.com/167884/amd-adopts-28-nm-bulk-manufacturing-in-2013.html

He could as well talk only of the yet to come Jaguar...
 

SiliconWars

Platinum Member
Dec 29, 2012
2,346
0
0
They officialy aknowledged 100W 2M4C SR , granted the 3.5ghz limitation is true then a 100W 4C SR would perform the same as a 100W piledriver 4C , seriously , why bother making a CPU that
would be not more power efficient , with all the hassle of a new node..?..

Well, when making a major change you have to start from somewhere. Bulldozer was a major change that had to start somewhere, it was only with Piledriver that it was semi-realised as a decent chip.

If the change from SOI to bulk is causing problems then AMD still doesn't really have much of an alternative but to go ahead with it. They can postpone for a while...refresh Trinity with Richland maybe...but sooner or later they have to make the switch to bulk as that is the road they are going down.

It's just a gut feeling I get and sadly my gut feelings tend to be near the mark. I'm prepared for Steamroller being another Bulldozer, at the very least I would suggest that expectations be tempered a bit. This is a big undertaking for AMD and they are being extremely quiet about it. There have been literally no performance estimates coming out of AMD for a long time.

One thing that set my alarm bells ringing was Andrew Feldman saying Berlin was "cool". I don't want to hear that it's "cool", I want to hear that it's "awesome". Cool can simply mean different, and obviously with the large IGP it's definitely got a "cool" factor about it in regards servers but I still really would much rather have read "awesome" instead.
 
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Abwx

Lifer
Apr 2, 2011
11,166
3,862
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One thing that set my alarm bells ringing was Andrew Feldman saying Berlin was "cool". I don't want to hear that it's "cool", I want to hear that it's "awesome". Cool can simply mean different, and obviously with the large IGP it's definitely got a "cool" factor about it in regards servers but I still really would much rather have read "awesome" instead.

The same words can have quite a different meaning
providing nothing is lost in the actual quotes.

A few of mr Feldman s claims :

About server piledrivers.

"What we are doing with the Warsaw Opteron is ripping out cost and power and increasing performance, and it is compatible with the existing G34 socket,"

The Warsaw chip will offer about 20 per cent higher performance per watt than the Opteron 6300, says Feldman
SRoller...

"Berlin is cool, and it uses a new Steamroller core from us and delivers tremendous compute and power efficiency," says Feldman. "When you have a huge amount of compute in a single-socket part, this is ideal for workloads where performance per watt per dollar and compute density per dollar are paramount."
A hint :

AMD is saying very little about the Steamroller core at this point, except that it offers double the performance of the Jaguar core and will max out with twice the memory capacity, too.
Finaly , an interesting trend with big consequences :

"Will ARM win in servers? And will AMD win with ARM? I think ARM wins in the long run. In the history of compute, small, lower cost, and higher volume always wins. And community always wins. ARM has lower power, but I don't think, in the end, that it wins because it is lower power. It wins because it is lower cost. It takes the process of making a CPU down from three and a half years and $350m and $400m down to 18 months and $30m."

http://www.theregister.co.uk/2013/06/18/amd_opteron_arm_server_chips/
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,688
1,222
136
When does Kaveri ship? Then we will know.
September-October to OEMs, November-Decemeber to DIYs.
You have to consider the overall change to bulk from SOI might have a negative impact as well, if only initially.
SOI doesn't effect clock rates nor how much logic you can put down. SOI only affects the end outcomes: Yields and Lifespan.
---
---
@Abwx, third quote:
Berlin - 128-bit DDR3 IMC
Kyoto - 64-bit DDR3 IMC
-
Berlin - 256-bit FMAC per core. (8 x 128-bit FMAC + 4 x 256-bit MMX)
Kyoto - 128-bit MAC per core. (4 x 128-bit ADD+MUL + 4 x 128-bit MMX)

As long as you don't use memory/gpu intensive benchmarks the A6-5200 outperforms the A10-5750M.
 
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Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
They officialy aknowledged 100W 2M4C SR , granted the 3.5ghz
limitation is true then a 100W 4C SR would perform the same as a
100W piledriver 4C , seriously , why bother making a CPU that
would be not more power efficient , with all the hassle of a new node..?...

The more I read about the possible outcome of SR on 28nm the more I can't help but think of the parallels to K10 Stars core (Llano) on 32nm versus how well the Stars core did with Thuban on 45nm.

What good did it do? It shrunk the die such that it cost AMD less to produce the chip. It didn't really improve clockspeeds (or power consumption it seemed) over what 45nm was already tweaked and tuned to deliver, but it (the 32nm shrink) did deliver a chip that cost less to manufacture.

So maybe that is what 28nm HKMG bulk Si is going to do for AMD over that of 32nm HKMG SOI, enable a smaller die-size and lower production costs but not really enabling much in terms of delivering a superior performing chip to the market versus that which 32nm is already capable of delivering.

Just speculation here, of course, I don't really know how it I going to pan out.
 
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