First Steamroller processor core exposure

[PPB]

Then you have no idea how rethoric works. Quoting a suposed authority on a subject only works if his area of expertise is totally related to the subject at hand.

I hate stating something most people knows, but chip design is really a vague definition considering the broad repertory of areas involved and the diversity of parallel projects done by a different CPU design teams. For example, you can be a chip designer in Intel's US team and probably know all the inner workings behind the Haswell design. Moreover, as you are asked about specific details involving Skylake's, you probably arent as well versed as someone from the Israeli team who is in fact working in it's design.

My metrics are very simple, and I already explained when I used Exophase's explanation on how Bobcat and Bulldozer's vector units aren't the same by simply the differences in key points using already published material. No need to break NDA's, no need to cite his track records on this forum nor anyone's elses.

 

[Vesku]

Perhaps it's Excavator, if real. If this is Steamroller you'd think they'd rush out at least a few 10s of thousands of AM3+ 4 module chips for the PR, rather than 220W TDP Vishera SKUs.

 

[NTMBK]

Perhaps it's Excavator, if real. If this is Steamroller you'd think they'd rush out at least a few 10s of thousands of AM3+ 4 module chips for the PR, rather than 220W TDP Vishera SKUs.

"Rush out"? I think you underestimate the amount of work involved in creating a new CPU! Even if the core is done, there is still lots and lots to do.

 

[galego]

That doesn't explain why you and others believe that less than a year is enough to revise the core architecture...

Steamroller A might just be an engineering sample where Steamroller B might be a newer engineering sample. Why you or anybody else believe that AMD heavily revised their uArch in less than a year is the question here.

I don't know. I only heard rumours that Jim Keller has been redesigning/improving Steamroller since the first week of his return. Some news site claims:

With the return of Jim Keller in AMD and the resurging engineering team, we're seeing a lot of developments coming back to play which were killed during the time when AMD was ruled by Hector J. Ruiz and Dirk Meyer.

Here's an alternative hypothesis:

-Hot Chips 2012 was talking about Steamroller
-Steamroller has 2x the performance of the Jaguar core
-There was never any 8 core or 6 core Steamroller, and the 4 core Kaveri was the plan from the start
-There is no Steamroller "a" and "b"

See this roadmap from April 2012 article (http://news.softpedia.com/news/AMD-s-New-Steamroller-Architecture-to-Bring-Significant-Performance-264918.shtml)?

This was 4 months before Hot Chips 2012. The part they talked at at HC2012 was the same part on these roadmaps- the 4 core APU, with no 8 core CPU counterpart and no 6 core APU. There was no "A" and "B".

This is all entirely feasible. However, the rumours of Steamroller A and B are persistent. And the six core kaveri was more than a mere rumour

A newer version of the NDA documents seen by us no longer include the references to a GDDR5 interface. The document detailing the GDDR5 interface was from last year, while the newer one we have seen is only a few months old. It seems AMDs engineers for some reason dropped GDDR5 in Kaveri. The possibility of models with 3 compute units (i.e. 6 cores) was removed as well. This is also reflected in the roadmap.

Did you forget that Kyoto only clocks at up to 2GHz, just like every other Jaguar part we currently know of?

Berlin will clock at as much as twice that. That alone would account for a 2x performance difference, probably higher.

No, I didn't forget, but then Steamroller would have the same performance than jaguar (per clock) and this makes little sense:

1. 4 jaguar cores perform as an i3 SB. This implies that Kaveri would be slower than Richland.
2. AMD would be substituting 8 PD core Opterons by Berlin. I.e. by something much slower.
3. It disagrees with the 30% IPC claimed in 2012.

 

[Vesku]

"Rush out"? I think you underestimate the amount of work involved in creating a new CPU! Even if the core is done, there is still lots and lots to do.

They've been demoing Kaveri for a while now. They even showed the actual Kaveri chip at Computex. They originally thought GF would finally have 28nm ready for a mid 2013 launch but we've seen how that worked out. I read that GF has finally shipped 10s of thousands of production 28nm wafers, certainly some of those must be Steamroller. Even sadder news for AMD if all those GF 28nm wafers went to Rockchip for their ARM SoCs.

 

[Abwx]

Even sadder news for AMD if all those GF 28nm wafers went to Rockchip for their ARM SoCs.

Seems that the high performances process is not fully mastered ,
hence AMD s being mute about a precise launch date.

 

[LegSWAT]

Seems that the high performances process is not fully mastered ,
hence AMD s being mute about a precise launch date.

Has AMD ever been more precise than H1/2?

 

[Exophase]

No, I didn't forget, but then Steamroller would have the same performance than jaguar (per clock) and this makes little sense:

1. 4 jaguar cores perform as an i3 SB. This implies that Kaveri would be slower than Richland.
2. AMD would be substituting 8 PD core Opterons by Berlin. I.e. by something much slower.
3. It disagrees with the 30% IPC claimed in 2012.

I am completely lost at what you're trying to say here. AMD says that Berlin will be 2x faster than Kyoto. We don't have a clock speed, I said it could be as much as 2x the clock speed based on prior products but it could also be lower. More importantly than that though, this "2x" figure is not supposed to be a precise measurement. It's a lot like when Apple said that iPhone 4S would have 2x the CPU power than iPhone 4. I'm sure there were benchmarks that showed a bigger improvement than that. Maybe they just wanted to round to a nice integer.

The reason why Berlin only comes in a 4-core APU variant is obvious - AMD is using Kaveri dies instead of making a new FX/server die.

Now the real question: what does any of this have to do with an alleged "B" version Steamroller core that has all of these extra execution resources that the "A" one we know about doesn't? Are you trying to say that Andrew Feldman really meant that Berlin will have 2x the IPC that Kyoto does?

 

[Abwx]

Has AMD ever been more precise than H1/2?

Spare us hollow comments , please , you know that you re
just spreading irrational claims.

Personal attacks are not allowed. And since you can't seem to stop, you can take some time off.
-ViRGE

 

[Vesku]

Seems that the high performances process is not fully mastered ,
hence AMD s being mute about a precise launch date.

Still just as sad news for AMD then, means GlobalFoundries is investing all that money AMD is paying them to perfect the 28nm process they will be marketing to non-AMD customers before perfecting the version of 28nm AMD needs.

 

[pelov]

Seems that the high performances process is not fully mastered ,
hence AMD s being mute about a precise launch date.

Same will go for the 20nm and 14nm-XM FinFET processes as well. Past 28nm, AMD is going to be in a rough spot. Given Intel's Haswell refresh, I suppose they're thinking the same thing the other foundries are.

What is interesting is that AMD, and other chip makers, may opt to just go with 14nm/16nm FinFET processes from GloFo/Samsung and TSMC respectively due to the relatively short time frame that the FinFET processes would arrive after 20nm. Sharing that same 20nm BEOL means less risk and a faster time-to-market.

 

[Idontcare]

Still just as sad news for AMD then, means GlobalFoundries is investing all that money AMD is paying them to perfect the 28nm process they will be marketing to non-AMD customers before perfecting the version of 28nm AMD needs.

I doubt it is happening that way down in the trenches TBH.

GloFo will be optimizing all the various sub-nodes in parallel, it is the nature of the job to do it that way.

It's just the nature of the device physics that makes it easier to optimize and polish the low-performance mobile versions of the node versus that of the highest performance version.

At TI we were a foundry like Samsung in that we developed process nodes for both internal use with internally designed ICs as well as external use with our fabless customers who wanted us to founder their ICs for them (Cyrix was one such prominent customer, as was SUN).

Now TI never had the internal need for silly high-performance (and high power-consumption) nodes once we abandoned the x86 market (circa 1997) as all our DSP chips were either destined for mobile apps or they were targeting high-performance but low-power designs (like oscilloscopes and so on)...however SUN always needed a version of the node which had an especially high performance capability (and accompanying high power-consumption budget).

In R&D we developed all three subnodes simultaneously, but it was much much easier to get that low-performance low-leakage/power subnode done with less resources and in less time versus the highest performance subnode.

And in fact traditionally there was a solid year between the time we released the low-power subnode to production versus when we could/would finally release the highest performing subnode to production.

It just took that much longer, that much more resources, to get those highest performing transistors to where they needed to be in terms of Idrive and Ioff as well as reliability and yields before they could be put into production. And as a result, the market release of SUN's products on any given node tended to run about 18 months behind the market release of TI's own products on the same node (albeit on a lower-power subnode).

So I wouldn't read into the AMD/GloFo situation that GloFo is prioritizing the non-AMD process flow over the AMD process flow just because the non-AMD process flow comes out before the AMD-optimized subnode.

In many ways it is just an unavoidable consequence of having a team do things in parallel while having one task be technically more challenging than the other task.

 

[galego]

I am completely lost at what you're trying to say here. AMD says that Berlin will be 2x faster than Kyoto. We don't have a clock speed, I said it could be as much as 2x the clock speed based on prior products but it could also be lower. More importantly than that though, this "2x" figure is not supposed to be a precise measurement. It's a lot like when Apple said that iPhone 4S would have 2x the CPU power than iPhone 4. I'm sure there were benchmarks that showed a bigger improvement than that. Maybe they just wanted to round to a nice integer.

The reason why Berlin only comes in a 4-core APU variant is obvious - AMD is using Kaveri dies instead of making a new FX/server die.

Now the real question: what does any of this have to do with an alleged "B" version Steamroller core that has all of these extra execution resources that the "A" one we know about doesn't? Are you trying to say that Andrew Feldman really meant that Berlin will have 2x the IPC that Kyoto does?

Feldman did not compare Berlin to Kyoto, but Steamroller core to Jaguar core. Berlin will be not 2x faster than Kyoto but much more.

If, as you suggest, the 2x performance of Steamroller is explained by a 2x higher clock then Feldman's claim is trivial, and performance looks ridiculous: Kaveri would be slower than Richland, Berlin would be much slower than Opteron...

Also his claim that "Berlin is cool, and it uses a new Steamroller core from us and delivers tremendous compute and power efficiency" wouldn't make sense. It would be like if anyone says that a hypothetical four Jaguar CPU at 3.2GHz delivers "tremendous compute", when the chip would be like an i3-SB.

Nobody said you that Feldman's 2x claim is "a precise measurement". I recall using the word "about" and similar when talking about performance.

Finally the reason why Berlin only comes in a 4-core CPU/APU variant is far from obvious. First, some sites are noting that substituting a 8C PD CPU by a 4C SR CPU means that SR gives a huge increase in performance:

The fact that AMD is listing Berlin as a replacement for the Opteron 3300 series says good things about the potential efficiency of the new hardware. The Current Opteron 3300 parts are a mixture of four and eight-core parts clocked at 1900MHz – 2800MHz. That should put the Berlin family ahead of the quad-core Opteron 3300s, but likely behind the eight-core Opteron 3380. While we expect Steamroller to be significantly faster than Piledriver, it’s unlikely to deliver a 2x performance improvement.

ExtremeTech prediction about the performance of 4C SR Berlin seems compatible with my prediction about 4C SR Kaveri.

Second, AMD is dropping the 4000/6000 series Opteron and substituting them by the new Warsaw CPU with 12/16 PD cores. It makes little sense that AMD is not releasing Warsaw 6C/8C version, unless Berlin 4C CPU is powerful enough to fill the space.

 

[Abwx]

Still just as sad news for AMD then, means GlobalFoundries is investing all that money AMD is paying them to perfect the 28nm process they will be marketing to non-AMD customers before perfecting the version of 28nm AMD needs.

They should benefit from a larger customers base that will
reduce amortizations costs for most of the process they ll use.

Same will go for the 20nm and 14nm-XM FinFET processes as well. Past 28nm, AMD is going to be in a rough spot. Given Intel's Haswell refresh, I suppose they're thinking the same thing the other foundries are.

What is interesting is that AMD, and other chip makers, may opt to just go with 14nm/16nm FinFET processes from GloFo/Samsung and TSMC respectively due to the relatively short time frame that the FinFET processes would arrive after 20nm. Sharing that same 20nm BEOL means less risk and a faster time-to-market.

Contrary to the general opinion i think that they wont
give up SOI at 28nm for AMD products since it would
cost less to just die shrink the current SOIprocess using
the same tools rather than implementing a new process
that would require redesign of CPU layout as well as
very different SPICE parameters that would mandate
a complete rework of the circuit dynamic caracteristics.

 

[Idontcare]

Same will go for the 20nm and 14nm-XM FinFET processes as well. Past 28nm, AMD is going to be in a rough spot. Given Intel's Haswell refresh, I suppose they're thinking the same thing the other foundries are.

What is interesting is that AMD, and other chip makers, may opt to just go with 14nm/16nm FinFET processes from GloFo/Samsung and TSMC respectively due to the relatively short time frame that the FinFET processes would arrive after 20nm. Sharing that same 20nm BEOL means less risk and a faster time-to-market.

In a lot of ways this is no different than how AMD internally handled the iteratively improved transistor timeline that was coming out of the 65nm R&D team and being rapidly implemented into 90nm production for existing 90nm CPUs at the time.

At the time AMD called this process CTI (continuous transistor improvement) and it was what enabled AMD to roll out better and better 90nm CPUs without requiring much in the way of a major CPU redesign in the meantime.

(there are lots of publicly available sources for this info, but my favorite is Goto-sans)

Now in the case of what GloFo is doing with their 20nm an 14XM is they are sharing the BEOL, so it is very similar to how they managed STT (shared transistor technology) spanning 90nm and 65nm.

In this case we could call it SMT (shared metallization technology) and it would appropriately fit within the existing vernacular established by AMD back in the 130/90/65nm timeframe.

And incidentally it was also CTI (and the resultant STT that came from it) that was to blame for the initial release of 65nm Athlon (and Phenom) chips clocking no better than their 90nm predecessors because the 90nm predecessors had the same transistors under the hood so to speak.

With CTI and STT you sort of robbed the thunder in terms of clockspeed and power-consumption from the next node to be released, but the next node at least still delivered a reduction in production costs because you got to shrink the die with the new node.

14XM will be just like a CTI step, only at 90nm AMD wouldn't have called a CTI step a new node, they just released it as "improved 90nm".

In this modern era where node labels are now leveraged all the more for marketing purposes they wouldn't dare release "improved 20nm" with finfets, it has to be labeled something far sexier (while diluting the value of having a numerically decrementing node label in the process).

 

[pelov]

In this modern era where node labels are now leveraged all the more for marketing purposes they wouldn't dare release "improved 20nm" with finfets, it has to be labeled something far sexier (while diluting the value of having a numerically decrementing node label in the process).

Has it ever been true, though? I've always looked at node labels as marketing, because a very good, high capacity, and great power characteristic 32nm node would be better than a spotty 28nm that's plagued with issues.

We throw around 'xxnm' labels quite a bit, but we have a tendency to forget it's how the mean of those chips perform - and the time frame, and the cost, and the capacity, and a million other things. The 'xxnm' is there just to represent the process, but it in no way defines it. Therefore, while some people see TSMC's and GloFo's (+alliance) 16/14nm + 20nm BEOL and FinFETS as 'cheating', I see no difference really...

 

[krumme]

Tsmc already have a huge cost advantage because of their business model vs Intel. What the customers need for some segments is better performance that can compete with Intel process performance. I dont think it matters for those segments the density stays the same - transforming into higher cost. As a business choice it makes perfect sense. The question is can tsmc deliver it at the promised timeline? I think history have shown we should be very critical asuming that.

 

[unon]

I think AMD is going for 28nm fdsoi and high ipc next (after kaveri). That leaked module shot is real. Here's why:

1) AMD said that they'd use 28nm for a longer time and though they'll stay 1 - 2 nodes behind intel they can compete by stuff like rcm and hdl. Plus new leaked glofo slide says HP to skip 20nm. Even ARM would be getting to 20nm only by 2015 so nothing new till 2016 for AMD?

2) Andrew Feldman said bulldozer was an unmitigated failure. This points to problems with the architecture itself. They'll probably keep cmt and go for high ipc, giving more space to the modules and clocks would be retained with fdsoi. afaik the goal of bulldozer was to have 10-12 cores in a thuban size die and have high clocks for ST perf, but bd power consumption is bad and density is apparently very bad too. Though trinity is more efficient than llano(adding process improvements) especially in mobile. Jaguar / arm is now for thoroughput oriented and big cores are latency oriented. SMT is probable or maybe some sort of Speculative multithreading for the 4 alu/agu's?


Steamroller should be a milder update(upto 30% ipc) but the kaveri es @ 1.8ghz points to high ipc. So 28nm fdsoi excavator with ddr4?

 

[pelov]

Everyone loves pictures.

The 14nm-XM process is built for lower power SoCs, and GloFo has been collaborating closely with ARM on that node. Whatever AMD gets for high power after 28nm is going to be seconds and not firsts. Back in 2010 AMD mentioned that the 28nm node would be a relatively 'long life' node, and you can see why.

Coincidentally, this doesn't exactly put AMD in a worse spot. With Intel refreshing Haswell and opting to focus instead on Atom, AMD's position isn't any worse. They might take a little longer to close the gap with respect to process, but AMD has also not mentioned any high power Steamroller Opteron/AM3+ derivatives. The low power nodes available to AMD are at the same time frame as ARM, it's just a matter of available capacity, but that's the case with any new node.

It used to be the SHP and equivalents would lead with the low power stuff trailing, but that's certainly not the case anymore. Face it, boys, we're just not that hip anymore*.



*unless by hip one means 'in need of a hip replacement

---

AMD has injected the Berlin Steamroller APU, Jaguar-derived APU, and ARM64 SoCs into the roadmap, but hasn't shown anything after that for 2015.

They've also extended Piledriver for traditional server throughout 2014, but have omitted entirely any mention of 20nm products (or 14nm-XM depending on the time frame. It would be logical to skip 20nm entirely). The above roadmap is a newer roadmap released a couple of months ago whereas the one above that (with the 20nm parts) is from October 2012. Given AMD's market share in traditional servers (sub-5%), it's plausible that they're pulling out of that race for good and only offering a Piledriver refresh with a bump in clock speed on a more mature process, or they've simply decided not to add the 20nm/14nm Excavator products on that roadmap since they'll be arriving 2015. With AMD adding Steamroller APUs and ARM64 to their lineup, I can definitely see AMD pulling out of the traditional server space (and in turn enthusiast desktop) completely.

It's just not worth the investment. I don't see why AMD would even want to attempt to crawl back and compete against Xeons when the consumer side (desktops) has taken a nosedive. It would make sense if you can supplement the R&D cost by offering it to two healthy markets, but that's just not the case anymore. The appeal of ARM64/A57 is that you don't have to spend billions and risk getting screwed to offer a competitive product, and Read doesn't look like an idiot to me.

 

[AtenRa]

Everyone loves pictures.

The 14nm-XM process is built for lower power SoCs, and GloFo has been collaborating closely with ARM on that node. Whatever AMD gets for high power after 28nm is going to be seconds and not firsts. Back in 2010 AMD mentioned that the 28nm node would be a relatively 'long life' node, and you can see why.

Coincidentally, this doesn't exactly put AMD in a worse spot. With Intel refreshing Haswell and opting to focus instead on Atom, AMD's position isn't any worse. They might take a little longer to close the gap with respect to process, but AMD has also not mentioned any high power Steamroller Opteron/AM3+ derivatives. The low power nodes available to AMD are at the same time frame as ARM, it's just a matter of available capacity, but that's the case with any new node.

It used to be the SHP and equivalents would lead with the low power stuff trailing, but that's certainly not the case anymore. Face it, boys, we're just not that hip anymore*.



*unless by hip one means 'in need of a hip replacement

---

AMD has injected the Berlin Steamroller APU, Jaguar-derived APU, and ARM64 SoCs into the roadmap, but hasn't shown anything after that for 2015.

They've also extended Piledriver for traditional server throughout 2014, but have omitted entirely any mention of 20nm products (or 14nm-XM depending on the time frame. It would be logical to skip 20nm entirely). The above roadmap is a newer roadmap released a couple of months ago whereas the one above is from October 2012. Given AMD's market share in traditional servers (sub-5%), it's plausible that they're pulling out of that race for good and only offering a Piledriver refresh with a bump in clock speed on a more mature process, or they've simply decided not to add the 20nm/14nm Excavator products on that roadmap since they'll be arriving 2015. With AMD adding Steamroller APUs and ARM64 to their lineup, I can definitely see AMD pulling out of the traditional server space (and in turn enthusiast desktop) completely.

It's just not worth the investment. I don't see why AMD would even want to attempt to crawl back and compete against Xeons when the consumer side (desktops) has taken a nosedive. It would make sense if you can supplement the R&D cost by offering it to two healthy markets, but that's just not the case anymore. The appeal of ARM64/A57 is that you don't have to spend billions and risk getting screwed to offer a competitive product, and Read doesn't look like an idiot to me.

GloFos 20nm is most probably a half node of 22nm (SOI ???) much like 28nm is to current 32nm SOI, 14XM is only meant for Low Power Mobile SoCs. AMD will not leave the x86 Server. Kaveri (Berlin) APUs will replace current 4,6,8 and 12 core x86 server parts. 16 core Opterons "Warsaw" will be available for high core density Could servers.

As far as i can see with the current information we have, AMD will have a new x86 big core in H1 2015 at 22/20nm (SOI ??).

 

[pelov]

GloFos 20nm is most probably a half node of 22nm (SOI ???) much like 28nm is to current 32nm SOI, 14XM is only meant for Low Power Mobile SoCs. AMD will not leave the x86 Server. Kaveri (Berlin) APUs will replace current 4,6,8 and 12 core x86 server parts. 16 core Opterons "Warsaw" will be available for high core density Could servers.

As far as i can see with the current information we have, AMD will have a new x86 big core in H1 2015 at 22/20nm (SOI ??).

Well, that's what I'm getting that. Will they?

The older roadmaps show a 20nm product in 2014/2015, but the more recent enterprise roadmap is devoid of any 'big core' non-APU products on anything under GloFo's 32nm SOI. GloFo has been offering 28nm for a while now with no reported issues (or at least rumors), so they've had the opportunity to release it. Hell, we're going to see Kaveri later this year but no mention at all of a Steamroller 'big core' product. Remember that whatever AMD gets as far as nodes go will also be late given the foundries' focus on low power.

With the addition of APUs and ARM64 to their server lineup, I just don't see why AMD would bother with the traditional server/desktop market at all. In fact, it's not even mentioned on the roadmaps anymore either. The enterprise sector always gets a 2-3 year roadmap showing what's on offer, because unlike the consumer side they tend to spend a lot more money (and there's higher margins up for grabs), but they also require stability. Enterprise buyers need to know what you've got coming in the next couple of years, otherwise you're not going to woo any customers onto a dead platform. If you don't have anything new in the next 2 years, and the last product you released was a year ago, then you should certainly start asking questions.

 

[krumme]

Gf ppt cartoon fun
I dont know how Mubadala can control their investments in amd and gf if they dont separate them completely?
If amd or gf bends their kpi to please mubadala and not the customers its going to be an even larger future mess. I dont know where mubada aquired the competences to know what is really going on. Perhaps they have some secret magic...

 

[LegSWAT]

Given it's not the process, but capacity, the delay speculation could rather end up as opportunity costs: Kaveri vs. ng console APU. Add in contractually laid out and warranted quantities delivered and an AMD exec need not think twice about which APUs to place under the Xmas tree and which not.

Spare us hollow comments , please , you know that you re
just spreading irrational claims.

Can you read this punctuation mark: "?" ? It's called a "question mark". If a "claim" is defined as "An assertion that something is true or factual", it most likely wouldn't be questioned in its very sentence. Yes, this is a claim.