First Steamroller processor core exposure

[Ajay]

My main area of expertise is "physical design". I started writing up a much longer reply but I probably shouldn't derail the thread even more . The Wikipedia article looks like a decent overview, but feel free to ask more questions in PMs or another thread.

Designing clock trees and routing - God bless you, that's got to be a nightmare in modern CPUs :awe:

 

[videoclone]

Exactly, it is what they are doing NOW the important thing, it reminds me of the Greek economic/politics Crisis (not Crysis 3 ). What happened in the last 30 years is of no immediate concern, we really have to focus on what we can do NOW and the years to come, to change the situation so we will have a better future.

Glad to be in Australia.. the only Western country to not go into the recension bucket. But we cap our CEO's and tax the hell out of rich people to give to the poor.. works well!

AMD lost allot of Intel's blackmail tactics and has what it has now. The future is looking better then it was but time will telll how things play out on the Top end CPU wars my fingers are crossed that 28nm Steamroller turns out to be a great cpu

 

[NostaSeronx]

http://farm4.staticflickr.com/3695/9106327470_f3570699c9_o.png
^-- No Labels.

http://farm6.staticflickr.com/5321/9104546631_4c7a4a023b_o.jpg
^ Labels.

"Prefetch?" Might be fuse boxes.

 

[Idontcare]

http://farm4.staticflickr.com/3695/9106327470_f3570699c9_o.png
^-- No Labels.

http://farm6.staticflickr.com/5321/9104546631_4c7a4a023b_o.jpg
^ Labels.

"Prefetch?" Might be fuse boxes.

Interesting. The beefier steamroller core is impressive. Are the side-by-side images presented at the same scale?

Are steamroller cores expected to be essentially the same physical size as piledriver cores?

 

[NostaSeronx]

Interesting. The beefier steamroller core is impressive. Are the side-by-side images presented at the same scale?

Just the same resolutions.

Are steamroller cores expected to be essentially the same physical size as piledriver cores?

It should be close to the same physical size but Steamroller is more square-ish than Bulldozer/Piledriver.

This is for reference it isn't exact or actual proportions.
Piledriver: 5 height, 8 width, 5 by 8. Quite Rectangular.
Steamroller: 7 height, 8 width, 7 by 8. Pretty Square.

Aligning the L2 cache parts from Steamroller to Piledriver:

Piledriver -

Steamroller -

^--looks like there is a second VSS part thing. (The thing next to the module and the L2 that looks like a small tic)

 

[Sequences123]

Is this SR, then?

 

[Idontcare]

Definitely going to be a sizable IPC boost then if they are throwing all those extra transistors into the core logic as provided by the xtor density boost of 28nm over 32nm.

Doesn't make it cheaper to manufacture though, in fact it will be all the more expensive (28nm wafers are more than 32nm) so hopefully AMD is going to be able to command a higher ASP from the chips.

 

[Pilum]

Is this SR, then?

Not according to AMDs SR presentation from last year. They didn't mention any additional ALUs/AGUs for the integer cores nor widened/doubled FPU pipelines. As the changes in the integer cores were explained (dedicated decoders for each core, better scheduler & memory pipeline), it seems unlikely they would forget to mention a doubling of execution units.

So this is probably an early Excavator prototype.

 

[NostaSeronx]

It is Steamroller, just so you know Pilum. There is a specific unit that on the 15h fam's processors that has been doubling per generation.
Bulldozer -> 32
Piledriver -> 64
Steamroller -> 128

If it was Excavator this unit would show double Steamroller, but it only shows double Piledriver.

 

[SlowSpyder]

I really hope an eight core 4.5GHz FX SR chip makes it to market.. looking unlikely though. :/

 

[Vesku]

I really hope an eight core 4.5GHz FX SR chip makes it to market.. looking unlikely though. :/

Indeed, if this is Steamroller a 4 module would make a great final chip for my AM3+ board. Great transistor trade up from 1090T.

 

[Centauri]

IMO, AMD is nearing the end of their competition with Intel in the mid/high-end desktop front. I think they'll walk away from the market as soon as they've built up enough business elsewhere for it to be a feasible abandonment.

In the meantime, I hope to see AMD realize that trying to catch Intel on TDP is a lost cause, because of the widening process gap, and instead just choose to go for balls to the wall performance. If it means 150w TDPs, then so be it. AMD needs margined desktop processors to fund their research efforts elsewhere. TDP wont keep AMD from getting those sales, but lack of competitive performance will.

 

[Arachnotronic]

It is Steamroller, just so you know Pilum. There is a specific unit that on the 15h fam's processors that has been doubling per generation.
Bulldozer -> 32
Piledriver -> 64
Steamroller -> 128

If it was Excavator this unit would show double Steamroller, but it only shows double Piledriver.

Okay, but again, did you miss the AMD HotChips presentation?

4x128bit FMACs per module wasn't listed.

 

[wlee15]

Okay, but again, did you miss the AMD HotChips presentation?

4x128bit FMACs per module wasn't listed.

However a 4 ALU/AGU in SR isn't out question since the presentation didn't describe what were in the integer pipelines. Also if I recalled correctly Intel's Northwood and Prescott respectivly had Hyper-threading and 64-bit disabled in the earlier versions so it's not unprecedented, although I can't see AMD going to 4 128-bit FMAC. It's probably in AMD's best interest to under promise and then try to over deliver.

 

[NTMBK]

Doesn't make it cheaper to manufacture though, in fact it will be all the more expensive (28nm wafers are more than 32nm) so hopefully AMD is going to be able to command a higher ASP from the chips.

I thought that SOI wafers were also more expensive than non-SOI ones- would the increased cost from 32-28 not balance out the reduced cost from dropping SOI?

 

[AtenRa]

After more evaluation, I now believe that the OP image is at 22/20nm and not 32/28nm.

 

[NostaSeronx]

I thought that SOI wafers were also more expensive than non-SOI ones- would the increased cost from 32-28 not balance out the reduced cost from dropping SOI?

SOI over time is cheaper than non-SOI.

4x128bit FMACs per module wasn't listed.

Actually, they somewhat stated double. Each FPU scheduler, dispatch, retire might only see 2 * 128b FMACs + 1 * 256b MMX units. http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.05 PM.png, notice it points to the FPU twice.

After more evaluation, I now believe that the OP image is at 22/20nm and not 32/28nm.

It is supposedly, 28-nm from TSMC. So, where TSMC said Intel wasn't 22-nm but 28-nm might have been true.
SOI = CPU-exlusive
Bulk = APU-exlusive
AMD APUs will be built at TSMC, while Semi-custom APUs will be built at GlobalFoundries. AMD CPUs on 28-nm have been delayed till Fab 1 at GlobalFoundries gets FD-SOI from IBM/STMicro. Reason for this info, Kaveri & Berlin are at TSMC because of Xbox One & Playstation 4 being fabbed at Fab 8, GlobalFoundries.

I really hope an eight core 4.5GHz FX SR chip makes it to market.. looking unlikely though. :/

To be reasonable, if there was an eight core Steamroller at stock it would have to be between, 1.6 GHz and 2.4 GHz. Any higher the voltage required to power all the logic units would push it past the 125 watt TDP mark.

Perf/Watt designs, mostly always have low clocks and high overclock-ability.

 

[sm625]

All that matters is can AMD deliver a clean double in L1 and L2 cache bandwidth? They are so far behind in L1 that it would take more than a clean double...

 

[Third_Eye]

SOI over time is cheaper than non-SOI.Actually, they somewhat stated double. Each FPU scheduler, dispatch, retire might only see 2 * 128b FMACs + 1 * 256b MMX units. http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.05 PM.png, notice it points to the FPU twice.It is supposedly, 28-nm from TSMC. So, where TSMC said Intel wasn't 22-nm but 28-nm might have been true.
SOI = CPU-exlusive
Bulk = APU-exlusive
AMD APUs will be built at TSMC, while Semi-custom APUs will be built at GlobalFoundries. AMD CPUs on 28-nm have been delayed till Fab 1 at GlobalFoundries gets FD-SOI from IBM/STMicro. Reason for this info, Kaveri & Berlin are at TSMC because of Xbox One & Playstation 4 being fabbed at Fab 8, GlobalFoundries.To be reasonable, if there was an eight core Steamroller at stock it would have to be between, 1.6 GHz and 2.4 GHz. Any higher the voltage required to power all the logic units would push it past the 125 watt TDP mark.

Why are you pushing FD-SOI again and again?

AMD has clearly stated as early as Mar2012 as well as Dec2012 WSA and multiple times in between that it is always going to use the Standard Manufacturing process at a given Global Foundries node. It is not going to use any special nodes like now.
Repeated once more in Q1-2013 Investor presentation

...Moving to standard 28nm process technology and significantly reducing reimbursements to GF for future research and development costs, a savings of ~$20M per quarter during the next several years...

The 32nm PD-SOI line is run specifically for AMD today (with a likelyhood that IBM might use it for its Power MPUs and/or the Nintendo Wii U SOC).

Kaveri APU (Steamroller CPU core) =>28nm Bulk HKMG GloFo
Jaguar CPU core derivatives till date => 28nm Bulk HKMG TSMC.

By Jaguar derivatives I mean Temash, Kabini today as well as PS4 and XB1 SOCs. Why would AMD suddenly manufacture a semi-custom APU with Jaguar CPU core at Global Foundries which has no 28nm product in the market, when the its multiple 28nm Jaguar core based products are being churned out at TSMC??

 

[Exophase]

Actually, they somewhat stated double. Each FPU scheduler, dispatch, retire might only see 2 * 128b FMACs + 1 * 256b MMX units. http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.05 PM.png, notice it points to the FPU twice.

Yeah, because both decoders need to be able to issue FPU instructions. How else could it work?

That diagram clearly shows 2x128-bit FPUs, there's no way you could legitimately interpret that to mean there's really 2x2x128-bit FPUs..

 

[Vesku]

Yeah, because both decoders need to be able to issue FPU instructions. How else could it work?

That diagram clearly shows 2x128-bit FPUs, there's no way you could legitimately interpret that to mean there's really 2x2x128-bit FPUs..

Is it possible its 2x128bit FPUs visible to the outside but more resources inside the chip that work on the given threads?

Imo, will be surprising if this is Steamroller and not Excavator.

 

[Exophase]

Is it possible it's 2x128bit FPUs visible to the outside but more resources inside the chip that work on the given threads?

I don't think the number of execution units is visible to the outside to begin with. The decoders encounter an FPU instruction and hand it off to the FPU if it has room in its buffers for it. The FPU schedules and executes it internally.

 

[Vesku]

I don't think the number of execution units is visible to the outside to begin with. The decoders encounter an FPU instruction and hand it off to the FPU if it has room in its buffers for it. The FPU schedules and executes it internally.

So is there any technical mess for developers they will cause if they decided to increase execution resources from what they had planned last year? (Or if they were under promising in their public information from last year.)

 

[galego]

It is supposedly, 28-nm from TSMC. So, where TSMC said Intel wasn't 22-nm but 28-nm might have been true.
SOI = CPU-exlusive
Bulk = APU-exlusive
AMD APUs will be built at TSMC, while Semi-custom APUs will be built at GlobalFoundries. AMD CPUs on 28-nm have been delayed till Fab 1 at GlobalFoundries gets FD-SOI from IBM/STMicro. Reason for this info, Kaveri & Berlin are at TSMC because of Xbox One & Playstation 4 being fabbed at Fab 8, GlobalFoundries.To be reasonable, if there was an eight core Steamroller at stock it would have to be between, 1.6 GHz and 2.4 GHz. Any higher the voltage required to power all the logic units would push it past the 125 watt TDP mark.

Not only TSMC, Globalfoundries and others have noticed that Intel nanometer is not everyone else nanometer. Globalfoundries claims:

Intel’s terminology doesn’t typically correlate with the terminology used by the foundry industry. For instance Intel’s 22nm in terms of the back-end metallisation is similar to the foundry industry’s 28nm. The design rules and pitch for Intel’s 22nm are very similar to those for foundries’ 28nm processes.

http://www.electronicsweekly.com/mannerisms/general/the-intel-nanometre-2013-02/

http://www.electronicsweekly.com/mannerisms/markets/intel-has-no-process-advantage-2012-10/

Why couldn't AMD pass the 125W TDP mark? Why not 150W as in the eXtreme i7? Why not an enthusiast Steamroller line with 220W?

 

[Exophase]

So is there any technical mess for developers they will cause if they decided to increase execution resources from what they had planned last year? (Or if they were under promising in their public information from last year.)

No.