First Steamroller processor core exposure

[mrmt]

Not only TSMC, Globalfoundries and others have noticed that Intel nanometer is not everyone else nanometer. Globalfoundries claims

A comment from one of the articles you posted here. You, as usual, didn't bother checking, but I'll repost here for the sake of the information. It is quite informative and might be an interesting reading for the honest posters here:

I’ll repeat some useful numbers I’ve given before at our events. As can be seen for SRAM the Intel 22nm is almost but not quite twice as dense as their 32nm process, whilst TSMC and GF processes fit in roughly to the Intel densities as given by the names of their nodes.

Once upon a time half the metal M1 pitch defined the node but in recent years metal pitch reduction has not kept pace with other features so fabs have tended to reference the node as the ratio to the density of SRAM at 65 or 90nm.

Certainly there is a LOT of market BS taking place as well (Intel included) but in reality Intel does lead the way in density at least.

Of course SRAM density isn’t everything but with BEOL limited by the desire to stay with single patterning, for logic the metal routing now begins to dominate over transistor size.

The drawn gate length is not really a relevant measure any more and in any case has never been the official definition of the node. It is generally used to set the performance of the transistor, shorter is faster whilst longer is slower but less leakage. The move to FinFETs allowed the performance and density of the next node to be achieved without going to shorter gate lengths which would have excessive leakage.

The additional complication of FD-SOI as a competing process technology will prove interesting. Despite the hype, FD-SOI SRAM densities won’t match the densest FinFET SRAMs at the same node, but leakage will be noticeably better, causing a definite process branch applicable to numerous applications.


The stats are :

SRAMs
(HP and special low power versions are larger for all fabs)

Intel 45nm SRAM cell – 0.346um^2
Intel 32nm SRAM cell – 0.171um^2
Intel 22nm SRAM cell – 0.092um^2

TSMC 40nm SRAM cell – 0.290um^2
TSMC 28nm SRAM cell – 0.127um^2
TSMC 20nm SRAM cell – 0.090um^2

GF 28nm SRAM cell – 0.120um^2

ST 28nm FD-SOI SRAM cell – 0.120um^2 (this is believed to be the version with no back-gate and uncompetitive leakage – 0.152um^2 for back-gate and lowest power/leakage but of course LP versions of other processes are also larger)


Metal pitch
(once upon a time half this was the node size but as can be seen the transistors have shrunk a lot more than the metal)

Intel 22nm metal pitch – 64nm
Intel 14nm metal pitch – 48nm

TSMC 28nm metal pitch – 64nm
TSMC 20nm metal pitch – 64nm

GF 14nm metal pitch – 48nm (predicted)


Contacted gate pitch
(this is a key dimension in that it is no point making transistor gates shorter unless you can reduce this number to match)

Intel 32nm contacted gate pitch – 112nm
Intel 22nm contacted gate pitch – 90nm (80nm with special processing)
Intel 14nm contacted gate pitch – unknown

TSMC 40nm contacted gate pitch – 160nm
TSMC 28nm contacted gate pitch – 118nm
TSMC 20nm contacted gate pitch – unknown
TSMC 14nm contacted gate pitch – unknown

GF 28nm contacted gate pitch – 113nm
GF 20nm contacted gate pitch – 80nm
GF 14nm contacted gate pitch – not relevant as BEOL is stated as being the same as 20nm. However this may change in due course.


I hope this helps

Mike Bryant

 

[nehalem256]

Not only TSMC, Globalfoundries and others have noticed that Intel nanometer is not everyone else nanometer. Globalfoundries claims:

SRAMs
(HP and special low power versions are larger for all fabs)

Intel 45nm SRAM cell – 0.346um^2
Intel 32nm SRAM cell – 0.171um^2
Intel 22nm SRAM cell – 0.092um^2

TSMC 40nm SRAM cell – 0.290um^2
TSMC 28nm SRAM cell – 0.127um^2
TSMC 20nm SRAM cell – 0.090um^2

From the comments. And yet the Intel SRAM density clearly shows 22nm as much denser than TSMC 28nm

 

[HurleyBird]

From the comments. And yet the Intel SRAM density clearly shows 22nm as much denser than TSMC 28nm

If anything, they're outperforming TSMC nm for nm - Intel 22nm ~= TSMC 20nm.

 

[Exophase]

Although TSMC said that SRAM shrunk only 40% from 28nm to 20nm (probably where that 0.090um^2 number came from) they actually claim 0.081um^2:

http://techon.nikkeibp.co.jp/english/NEWS_EN/20130226/268112/?SS=imgview_e&FD=48575398&ad_q

Intel's 22nm would still be denser if scaled per the node name, though.

 

[Idontcare]

It isn't enough to just compare physical dimensionality and densities, of course, as you must also factor in capability in terms of clockspeeds, power-consumption, and reliability on some normalized basis.

 

[Exophase]

It isn't enough to just compare physical dimensionality and densities, of course, as you must also factor in capability in terms of clockspeeds, power-consumption, and reliability on some normalized basis.

Yeah, I should have added "not that that really means anything."

It is a little strange that the usual density scaling, at least for SRAM, is going way down with TSMC's 20nm. Do you know if it has to do with the much more restrictive design rules?

I've also heard rumors that the node brings almost no power savings, although some other claims contradict this.

 

[SocketF]

Why are you pushing FD-SOI again and again?

AMD has clearly stated as early as Mar2012 as well as Dec2012 WSA and multiple times in between that it is always going to use the Standard Manufacturing process at a given Global Foundries node. It is not going to use any special nodes like now.
Repeated once more in Q1-2013 Investor presentation

...Moving to standard 28nm process technology and significantly reducing reimbursements to GF for future research and development costs, a savings of ~$20M per quarter during the next several years...

"Standard" doesnt mean bulk, standard means anything GF can offer and we (AMD) dont have to pay for it.
Furthermore AMD's CEO stated in another speech that they want to reduce the costly mask-layers, that is typical for SOI-processes. Said that, FD-SOI is not a given as nobody knows to which time-frame / process the mask-layer reference referred to.

ST 28nm FD-SOI SRAM cell – 0.120um^2 (this is believed to be the version with no back-gate and uncompetitive leakage – 0.152um^2 for back-gate and lowest power/leakage but of course LP versions of other processes are also larger)

Just for info: Last time I checked the back-biased versions had the lower cell sizes, seems the bigger cells are a "feature" of the pure LP-process. GF also mentioned it somewhere else that the cell size will shrink when using BBias. Thus it is not that bad.
FD-SOI really seems great at 20nm, no Finfet-design needed, low-leakage, high-performance with back-bias, better yields because of less doping, and then they even claim less process costs ... oh and then the density ... 20nm FD-SOI (aka "14nm") is still on Gate-First.

 

[galego]

I believed the important part were the articles linked, but if some of you are going to quote comments to the articles, then quote also the ones where the author tries to receive an official reply from Intel to the questions "What does 22nm measure in its 22nm process?" "So 22nm doesn’t relate to anything in particular?" "Do you know why that number was chosen?" The answer he received was: "Quite honestly I don't know."

And if you are not completely shocked by this reply, then find in the comments the quote by Scott Thompson, a former Intel fellow: "Intel's 22-nm node is really 26 nm, so if Intel does new math, so will we".

The fact that Intel 22nm equates to other's 28nm for some stuff or to 26nm for other stuff, fits very well in Intel's lack of answer to what is really measuring 22nm in their supposed 22nm process.

 

[Exophase]

How about also asking what it is about their 16nm and 14nm FinFET processes that justify those names at TSMC and Global Foundries respectively. At least Intel's 22nm represents the expected increase in density for similar designs over its predecessors, the same can't be said for those other two.

Of course we don't even know who David Manners got that "I don't know" response from. It could have been a PR rep who didn't know the first thing about Intel's engineering.

 

[NostaSeronx]

Kaveri APU (Steamroller CPU core) =>28nm Bulk HKMG GloFo

TSMC

By Jaguar derivatives I mean Temash, Kabini today as well as PS4 and XB1 SOCs. Why would AMD suddenly manufacture a semi-custom APU with Jaguar CPU core at Global Foundries which has no 28nm product in the market, when the its multiple 28nm Jaguar core based products are being churned out at TSMC??

IBM was the actual one who built the semi-custom chips through a co-op with AMD. IBM's Foundries are exclusively; GlobalFoundries. IBM gets the design royalties, while AMD gets the license royalties.

Why are you pushing FD-SOI, again and again?

AMD's first processor that was suppose to be on 28-nm Bulk was cancelled. That processor was the successor to the "Orochi" design called "Viperfish." So, far this design or it's successor won't show up till after H2 2014.

Interlagos - 2011 - 2012
Abu Dhabi - 2012 - 2014
Warsaw - 2014 - 2015

All 32-nm PD-SOI, so either AMD is waiting for a SOI process or AMD is waiting for 20-nm. It is a lot more believable with AMD waiting for a SOI process, than waiting for 20-nm. AMD also stated before they are transitioning nodes slower to maximize on the process. 32-nm PD-SOI has more clock potential than 28-nm Bulk, you know the rest with FD-SOI.

 

[itsmydamnation]

so what do we think? with GF 28nm being all but MIA and super late will we see a 4 module SR at all? maybe we are only going to see Kaveri and then a 4+ module EX on 20nm hopefully late next year.

 

[NostaSeronx]

with GF 28nm being all but MIA and super late will we see a 4 module SR at all?.

I'm dividing this in half.

1st part - GlobalFoundries 28-nm.
GlobalFoundries 28-nm is not MIA, it is insignificant. The reason for that was the only yields at GlobalFoundries could get in 2012/2013 was SLP. As of now, GF are getting yields for HP/HPP, but it isn't very bountiful. This basically means Playstation 4 and Xbox One won't be able to meet initial demand.

2nd part - Steamroller 4 module.
In 2012, we consumers were suppose to get a 5 module, Piledriver, for servers/enthusiasts. With the immediate successor for 2013 to be a 5 module, Steamroller, for servers/enthusiasts. Expectations for servers, now should be 6 to 8 modules on a single die, while 12 to 16 modules on MCM.

 

[Idontcare]

It is a little strange that the usual density scaling, at least for SRAM, is going way down with TSMC's 20nm. Do you know if it has to do with the much more restrictive design rules?

The benefits of biting the bullet and taking on double-patterning. More spendy but gives you much better density.

It is a one-time benefit though, Intel took theirs already a while back.

I've also heard rumors that the node brings almost no power savings, although some other claims contradict this.

They are struggling there, definitely need finfet for 20nm.

16nm is basically what 20nm was supposed to be. But rather than delay 20nm until the finfet xtors are ready, they are going to release 20nm "on schedule" and then release the real deal 2yrs later so they can claim "on time" with 16nm...when reality is they are going to be 2yrs late with 20nm.

 

[carop]

It is quite informative and might be an interesting reading for the honest posters here:

Sadly, those pitch numbers are incorrect. Intel is not using double patterning on their 22 nm node. You would need double patterning for any pitch smaller than 80 nm using single-pattern lithography. Furthermore, a 48 nm pitch requires triple patterning using 193 nm immersion lithography.

The correct metal pitch numbers are publicly available really.

*** Metal Pitch ***

Intel 22 nm metal pitch - 90 nm
Intel 14 nm metal pitch - 64 nm

TSMC 20 nm metal pitch - 64 nm
TSMC 16 nm metal pitch - 64 nm

GF 20 nm metal pitch - 64 nm
GF 16 nm metal pitch - 64 nm

The following slide is from Mark Bohr, the Senior Intel Fellow:

 

[carop]

The benefits of biting the bullet and taking on double-patterning. More spendy but gives you much better density.

It is a one-time benefit though, Intel took theirs already a while back.

There is a technical reason for using double patterning. The smallest pitch that could be produced using the current 193 nm immersion lithography is 80 nm.

The smallest pitch on Intel's 22 nm node is 90 nm (80 nm with special processing). Yes, Intel will have to "bite the bullet" on their 14 nm node.

Furthermore, the foundries as well as Intel will have to "bite the bullet" three times on their 10 nm nodes if EUVL (Extreme ultraviolet lithography) is still not ready. This is because the smallest pitch that can be produced with double patterning lithography is 48 nm.

You appear to think otherwise but the White Knight of Santa Clara is not immune from to the basic laws of physics.

 

[Arachnotronic]

There is a technical reason for using double patterning. The smallest pitch that could be produced using the current 193 nm immersion lithography is 80 nm.

The smallest pitch on Intel's 22 nm node is 90 nm (80 nm with special processing). Yes, Intel will have to "bite the bullet" on their 14 nm node.

Furthermore, the foundries as well as Intel will have to "bite the bullet" three times on their 10 nm nodes if EUVL (Extreme ultraviolet lithography) is still not ready. This is because the smallest pitch that can be produced with double patterning lithography is 48 nm.

You appear to think otherwise but the White Knight of Santa Clara is not immune from to the basic laws of physics.

The "White Knight" of Santa Clara sunk $4B into ASML in order to get the EUV ball rolling at least

 

[NTMBK]

TSMCIBM was the actual one who built the semi-custom chips through a co-op with AMD. IBM's Foundries are exclusively; GlobalFoundries. IBM gets the design royalties, while AMD gets the license royalties.AMD's first processor that was suppose to be on 28-nm Bulk was cancelled. That processor was the successor to the "Orochi" design called "Viperfish." So, far this design or it's successor won't show up till after H2 2014.

Interlagos - 2011 - 2012
Abu Dhabi - 2012 - 2014
Warsaw - 2014 - 2015

All 32-nm PD-SOI, so either AMD is waiting for a SOI process or AMD is waiting for 20-nm. It is a lot more believable with AMD waiting for a SOI process, than waiting for 20-nm. AMD also stated before they are transitioning nodes slower to maximize on the process. 32-nm PD-SOI has more clock potential than 28-nm Bulk, you know the rest with FD-SOI.

Nonsense.

If you actually listen to what AMD says, they say that:

"So with respect to SOI (Silicon On Insulator), we made statements that on 28-nanometer, all of our products will be bulk."

and:

"If you look at the roadmaps that we have presented at Financial Analyst Day, there is a 28-nanometer successor product to Trinity on the roadmap that we will ramp next year, and that is also manufactured at GLOBALFOUNDRIES."

This was from a conference call with Seifert, the CFO.

http://www.brightsideofnews.com/new...lk-at-gf2c-more-details-from-the-new-wsa.aspx

Also, why on earth would IBM be getting design royalties? (Except for the XBone APU, where I gather that they were involved in the ESRAM.)

 

[SocketF]

If you actually listen to what AMD says, they say that:

Given AMD's track-record of their statements I would say that it doesnt make sense to listen to them. Any statement that is older than 6 months is not worth much.
Since that "bulk" statement, Kaveri got delayed, there is a rumored Kaveri B and GF mentioned 32/28SHP processes on their roadmap.

Altogether there is - according to my opinion - the possibility for Kaveri using GF's 28nm PD-SOI process.

 

[galego]

Sadly, those pitch numbers are incorrect. Intel is not using double patterning on their 22 nm node. You would need double patterning for any pitch smaller than 80 nm using single-pattern lithography. Furthermore, a 48 nm pitch requires triple patterning using 193 nm immersion lithography.

The correct metal pitch numbers are publicly available really.

*** Metal Pitch ***

Intel 22 nm metal pitch - 90 nm
Intel 14 nm metal pitch - 64 nm

TSMC 20 nm metal pitch - 64 nm
TSMC 16 nm metal pitch - 64 nm

GF 20 nm metal pitch - 64 nm
GF 16 nm metal pitch - 64 nm

Which puts Intel’s 14nm process pretty much on a par with the foundry industry’s 20 nanometre process, and behind TSMC’s 16 nanometre finfet process and Globalfoundries’ 14nm process.

As noted in one of the articles linked in #149.

 

[AtenRa]

I dont believe AMD will use FD-SOI at 28nm or 22/20nm.

 

[Third_Eye]

"Standard" doesnt mean bulk, standard means anything GF can offer and we (AMD) dont have to pay for it.
Furthermore AMD's CEO stated in another speech that they want to reduce the costly mask-layers, that is typical for SOI-processes. Said that, FD-SOI is not a given as nobody knows to which time-frame / process the mask-layer reference referred to.

Agreed. But at 28nm the standard process is 28nm HKMG Bulk. All announcements from AMD, Rockchip, ARM (collaboration) etc all talked about 28nm HKMG. From the GF website

http://www.globalfoundries.com/technology/28nm.aspx

..The 28nm technologies are based on bulk silicon substrates, and are designed for a wide variety of applications from high performance such as graphics and wired networking to mobile computing and digital consumer to low power wireless mobile applications that require long battery lifetime...

There is not a single mention of 28nm FDSOI anywhere.

As early as 2012, in the final spinoff of remainig AMD equity in GloFo, AMD said (Thomas Seifert) that all its 28nm products in GF would be on bulk.

Looking at the the basic standstill of MPU variants even in 2014 at 32nm PD-SOI(Warsaw MPUs), we can safely assume that

a) there is no magical 28nm FD-SOI node.
b) Even if there is one AMD is not using it even till 2014

BTW we all know that STM licensed its 28nm FD-SOI to GF. We do not know if GF even committed to build products using that technology or if so what volume. All follow-ups to that licensing state only things like "STM confident of a deal to manufacture products at 28nm FDSOI at GF", "STM finalizing agreement with GF to build 28nm FDSOI products in mass " etc.

 

[NostaSeronx]

We do not know if GF even committed to build products using that technology or if so what volume.

Risk Production - Q2-Q3 2013
Volume Production - Q4 2013-Q1 2014

Basically, if there is a FX Steamroller, it would be in the, 2H of 2014. With server variants in the, 1H of 2015. On 28-nm FD-SOI at Fab 1 from GlobalFoundries.

If you actually listen to what AMD says, they say that

If you actually listened to what AMD has said. You would know it meant bulk for only APUs. If it was for CPUs, "Warsaw" would be on 28-nm Bulk not 32-nm PD-SOI.

 

[Idontcare]

There is a technical reason for using double patterning. The smallest pitch that could be produced using the current 193 nm immersion lithography is 80 nm.

The smallest pitch on Intel's 22 nm node is 90 nm (80 nm with special processing). Yes, Intel will have to "bite the bullet" on their 14 nm node.

Furthermore, the foundries as well as Intel will have to "bite the bullet" three times on their 10 nm nodes if EUVL (Extreme ultraviolet lithography) is still not ready. This is because the smallest pitch that can be produced with double patterning lithography is 48 nm.

You appear to think otherwise but the White Knight of Santa Clara is not immune from to the basic laws of physics.

Not sure where you are going with all that but Intel already adopted double-patterning way back in the time of 65nm and 45nm.

The foundries have pushed back on it until now and won't adopt it until 20nm.

GlobalFoundries: Double Patterning to Reach 20 nm

"Using double patterning overcomes lithography limitations to fully realize the potential of a 20 nm process by manufacturing alternate tracks of metal in two separate steps," Tan wrote. "Double patterning requires extra masks, along with a colorized layout decomposition process to determine how layout features will be mapped to masks. However, double patterning is primarily needed for lower metal layers, and is not required for every layer."

In the meantime this has driven a fundamental capability gap between Intel and the foundries in terms of cost/wafer (Intel being higher) and process capability (density, yield, clockspeeds, power all in Intel's favor).

That gap will close with the adoption of multi-patterning, at the expense of making foundry wafers even more expensive, and eventually with 16nm/14nm the introduction of finfets.

Intel intends to adopt quadruple-patterning for select masks when it launches 10nm.

The 10-nm process would debut in 2015 or later. It would require quadruple patterning for some mask layers but “it’s still economical,” said Mark Bohr, director of Intel’s technology and manufacturing group, speaking to EE Times after a talk at the Intel Developer Forum here.

If the foundries don't follow suit at their 10nm-equivalent nodes then you can expect to continue to see them fall behind Intel in terms of density, clockspeed, power, and yields.

You can't have it all unless you are prepared to pay for the privilege. If you want leading edge electrical parameters on your process node then you have to step up and embrace the more complicated process technology features like finfets and multiple-patterning.

 

[NTMBK]

If you actually listened to what AMD has said. You would know it meant bulk for only APUs. If it was for CPUs, "Warsaw" would be on 28-nm Bulk not 32-nm PD-SOI.

My quotes say that a) all 28nm will be bulk and b) the successor to Trinity will be at GlobalFoundries on 28nm. Not sure what another touch up of Piledriver has to do with either of those statements.

 

[Third_Eye]

My quotes say that a) all 28nm will be bulk and b) the successor to Trinity will be at GlobalFoundries on 28nm. Not sure what another touch up of Piledriver has to do with either of those statements.

Nonsense.

If you actually listen to what AMD says, they say that:

and:

This was from a conference call with Seifert, the CFO.

http://www.brightsideofnews.com/new...lk-at-gf2c-more-details-from-the-new-wsa.aspx

Also, why on earth would IBM be getting design royalties? (Except for the XBone APU, where I gather that they were involved in the ESRAM.)

If you look at the answers or responses from Seronx your head will spin faster than planet mercury rotating on its own axis ;-). Anything that can be eliminated by even basic logic would be replied with more high-tech blah!blah!

All SOCs of the last generation consoles were fabbed at IBM. They all had some kind of IBM CPU cores

Wii - PowerPC Broadway + ATI Hollywood graphics
XB - PowerPC Xenon + ATI Xenos graphics
PS3 - PowerPC Cell + NVIDIA licensed Graphics

Even in the above cases, it is left to the manufacturer (Nintento, MS, Sony) to actually design the SOC themselves at a particular manufacturing node at IBM Micro electronics to fab.

So the statement that IBM was the actual one who built the semi-custom chips through a co-op with AMD is BS at many levels. It is also served with a turd topping of
IBM's Foundries are exclusively; GlobalFoundries. IBM gets the design royalties, while AMD gets the license royalties.
whatever it means

In the current/new generation consoles, is what we call it semi-custom APU and that too only for PS4 and XB1 where in AMD designed for Sony and MS respectively the whole SOC . Wii U still follows the prior model of Nintendo integrating a Expresso PowerPC core and a licensed ATI Latte graphics core.

It is as simple as that.....

After providing even proofs from GF website as to all 28nm products will be in Bulk HKMG and 28nm Bulk HKMG is the successor to the first generation 32nm PD-SOI HKMG, still ppl are waving a 28nm FD-SOI pixie dust again and again and some even 28nm PD-SOI.