First Steamroller processor core exposure

[NTMBK]

All SOCs of the last generation consoles were fabbed at IBM. They all had some kind of IBM CPU cores

Wii - PowerPC Broadway + ATI Hollywood graphics
XB - PowerPC Xenon + ATI Xenos graphics
PS3 - PowerPC Cell + NVIDIA licensed Graphics

Even in the above cases, it is left to the manufacturer (Nintento, MS, Sony) to actually design the SOC themselves at a particular manufacturing node at IBM Micro electronics to fab.

Not true, actually. Certainly the final revision of the 360, where the CPU + GPU were combined into a single die, was fabbed at none other than GloFo. (I believe that Chartered were also a second source from the start.) And the 360 CPU was certainly designed by IBM, not Microsoft! Microsoft gave requirements and input, but IBM did the design work. IBM also design the PPE of the Cell, but the overall chip design was indeed a collaboration with Sony (and Toshiba).

 

[Third_Eye]

Risk Production - Q2-Q3 2013
Volume Production - Q4 2013-Q1 2014

Basically, if there is a FX Steamroller, it would be in the, 2H of 2014. With server variants in the, 1H of 2015. On 28-nm FD-SOI at Fab 1 from GlobalFoundries.If you actually listened to what AMD has said. You would know it meant bulk for only APUs. If it was for CPUs, "Warsaw" would be on 28-nm Bulk not 32-nm PD-SOI.

LOL!
http://www.amd.com/us/press-releases/Pages/amd-unveils-2013june18.aspx

Historically the FX series is the non-server variant of the server 1P MPU. Steamroller cores do not end up in FX series declared for even 2014.

If so there is no reason for Warsaw Server MPUs to remain at 32nm PD-SOI in 2014. One would think the natural path to progression would be to 28nm FD-SOI for them but that ain't happening. With the concentration on HSA, OCL and fusion of GPU compute, AMD is just trying to mint money out of the 32nm PD-SOI for all its worth by creating the new "5GHz" thermal heaters and for customers who have sunk money into the socket G2 platforms, provide a small upgrade path to their existing infrastructure.

And Rory R is not willing to chase small markets from his standpoint and so you can basically write off a Steamroller based FX as a low volume part and unless some OEM orders a huge quantity of that, it is a non-starter....

 

[mrmt]

Basically, if there is a FX Steamroller, it would be in the, 2H of 2014. With server variants in the, 1H of 2015. On 28-nm FD-SOI at Fab 1 from GlobalFoundries.If you actually listened to what AMD has said. You would know it meant bulk for only APUs. If it was for CPUs, "Warsaw" would be on 28-nm Bulk not 32-nm PD-SOI.

How large is the size of AMD FX and Server chips production runs? Would GLF have any chance of making money establishing a production line only for these AMD chips?

 

[SocketF]

Agreed. But at 28nm the standard process is 28nm HKMG Bulk.

That's your interpretation, I posted my interpretation above. I could also add one: If they meant bulk, why didnt they say bulk?
"Standard" is just a blurry term to leave all options open and available.

All announcements from AMD, Rockchip, ARM (collaboration) etc all talked about 28nm HKMG. From the GF website

http://www.globalfoundries.com/technology/28nm.aspx

..The 28nm technologies are based on bulk silicon substrates, and are designed for a wide variety of applications from high performance such as graphics and wired networking to mobile computing and digital consumer to low power wireless mobile applications that require long battery lifetime...

Yes and where is the quote from AMD about what they mean with standard? Quotes form another company (Rockchip), wont help us. I understand your POV, you think standard is what the majority takes, but I argue that it is anything what GF offers.
Non-standard for me are just the old SHP processes, that AMD had to pay GF for, as only AMD used it. So it obviously was a special process not a standard process. That's the connection where I think "standard" is equal to "we (=AMD) dont have to pay for it".

There is not a single mention of 28nm FDSOI anywhere.

Ahh 28nm ... yes in that case I dont see it myself as an option. It probably came too late. If I speak of FD-SOI then I mean 20nm. The manufacturing agreement with GF is also valid on the 20nm node (now called 14nm), so AMD could use it for Excavator. Prototyping starts Q3/13, risk production in early H2/14, sounds good enough for a FD-SOI chip from AMD for some time in 2015. Also lets not forget that AMD has canceled their own 20nm SHP-process.

As early as 2012, in the final spinoff of remainig AMD equity in GloFo, AMD said (Thomas Seifert) that all its 28nm products in GF would be on bulk.

Yes and Seifert is still in the Board of AMD. What I want to say: People change, as do plans, especially at AMD :ninja:

and some even 28nm PD-SOI.

It was mentioned in February by a GF guy who said that "this is the process that AMD uses to make their chips." Why should I not mention it here?

 

[Exophase]

The benefits of biting the bullet and taking on double-patterning. More spendy but gives you much better density.

It is a one-time benefit though, Intel took theirs already a while back.

But the improvement in density going from TSMC's 28nm to 20nm, at least for their SRAM cell, is much lower than the improvement going from 40nm to 28nm. Like you say, double patterning was first implemented at 20nm. So what's the deal here?

They are struggling there, definitely need finfet for 20nm.

16nm is basically what 20nm was supposed to be. But rather than delay 20nm until the finfet xtors are ready, they are going to release 20nm "on schedule" and then release the real deal 2yrs later so they can claim "on time" with 16nm...when reality is they are going to be 2yrs late with 20nm.

Some (outside of TSMC themselves, for instance Xilinx) are claiming products on TSMC's so-called 16nm by the end of 2014. That may be too optimistic, but 2016 seems overly pessimistic. This is supposed to be out faster than the usual node transition since it isn't really a full one.

 

[chernobog]

Steamroller FX arriving in H2 2014?

Bad news for AMD users, but look at the positive side... AMD can work further on Steamroller or even jump to TSMC's 20nm if possible...

 

[Idontcare]

But the improvement in density going from TSMC's 28nm to 20nm, at least for their SRAM cell, is much lower than the improvement going from 40nm to 28nm. Like you say, double patterning was first implemented at 20nm. So what's the deal here?

Remember "40nm" was actually their supposedly cancelled 45nm that was actually just 45nm rebranded as 40nm and ramped to production nearly a year late.

At 32 minutes into the call, Altera CEO John Daane corrected financial analyst Uche Orji about the next generation: "Our 40nm, and it is 40 not 45...we did call it 45 earlier but only because TSMC had not announced that it was really 40. They did that a few weeks ago, so I can tell you that we are the lead customer on the 40nm process technology...both software as well as components will be shipped this year."

link

TSMC is the king of claiming they came in on time, but the way they do it is by claiming they cancelled a node and are skipping ahead to the next one.

40 to 28 looks great on paper because it really is a 45 to 28 jump.

The historical reasoning why this happened has to do with the CEOs and the R&D director. Both stepped down after 65nm, the new guys totally botched the 45nm development timeline and got replaced to get 28nm back on track.

And who did they replace them with? The same guys that stepped down after 65nm. Morris Chang came back.

 

[Third_Eye]

That's your interpretation, I posted my interpretation above. I could also add one: If they meant bulk, why didnt they say bulk?
"Standard" is just a blurry term to leave all options open and available.

.
Go up 1 level on the link I provided
http://www.globalfoundries.com/technology/leading_edge_tech.aspx

... Our 28nm technologies are based on industry-standard bulk silicon substrates and utilize the same HKMG gate stack as our 32nm-SHP. The 28nm High Performance Plus (HPP) and Super Low Power (SLP) technologies are designed for a wide variety of applications from high-performance graphics and wired networking to low-power wireless mobile applications that require long battery lifetime....

Ahh 28nm ... yes in that case I dont see it myself as an option. It probably came too late. If I speak of FD-SOI then I mean 20nm. The manufacturing agreement with GF is also valid on the 20nm node (now called 14nm), so AMD could use it for Excavator. Prototyping starts Q3/13, risk production in early H2/14, sounds good enough for a FD-SOI chip from AMD for some time in 2015. Also lets not forget that AMD has canceled their own 20nm SHP-process.

http://www.globalfoundries.com/technology/pdf/GF-14XM-Press-FINAL.pdf
Refer Page 6 & Page 7

Yes and Seifert is still in the Board of AMD. What I want to say: People change, as do plans, especially at AMD :ninja:
It was mentioned in February by a GF guy who said that "this is the process that AMD uses to make their chips." Why should I not mention it here?

I quoted Seifert to indicate that ever early as Feb2012 it was clear that AMD is going to manufacture all its 28nm products in Bulk Silicon across both the foundries TSMC as well as GF.

When STM licensed FD-SOI to GF even allowing GF to extend it to other clients of it(Jun 2012), I was looking to see if there was any change in AMD's plans for its 28nm products at GF.

But in Dec 2012 WSA the "Standard " nomenclature came to the picture. So it has been clear all along that FD-SOI is no go for AMD at 28nm.

Unless GF as a part of the IBM, GF,Smsng consortium decide to use a SOI based node, AMD will not use it. And the last time I heard IBM mouth off, it was like 16nm when the consortium will think of going SOI as its standard technology.

Just a note FD-SOI 28nm is proprietary to ST Microelectronics and is home grown. So eventhough STM is a part of IBM consortium, it owns this and has the rights to the process.

 

[Exophase]

Remember "40nm" was actually their supposedly cancelled 45nm that was actually just 45nm rebranded as 40nm and ramped to production nearly a year late.

TSMC is the king of claiming they came in on time, but the way they do it is by claiming they cancelled a node and are skipping ahead to the next one.

40 to 28 looks great on paper because it really is a 45 to 28 jump.

Oddly not what you said here: http://forums.anandtech.com/showpost.php?p=26855940&postcount=14

So 28nm isn't what 32nm was supposed to be?

I remember David Kanter once assured me that TSMC 28nm would have no density advantage vs Intel's 32nm (Medfield et al). I think this probably did not end up being the case, though..

AFAIK there actually was a difference between 45nm and 40nm for low power variants (where they did actually offer the former) but I'm not sure what the word was on SRAM cell size.

 

[carop]

Not sure where you are going with all that but Intel already adopted double-patterning way back in the time of 65nm and 45nm.

I am talking about the metal interconnect.

The local metallization layers of logic products are historically the densest layouts to lithographically pattern and are key drivers of product density (and therefore cost).

Due to delays in extreme-UV (EUV) lithography the foundries are using DPT (double-patterning technology) at their 20 nm node because the smallest pitch that can be produced using 193 nm immersion lithography is 80 nm.

The foundries and Intel have been using different metal pitch sizes up until the 14 nm node. Here are the details for your reference:

*** Metal Pitch ***

Intel 32nm metal pitch - 113nm
Intel 22nm metal pitch - 90nm
Intel 14nm metal pitch - 64nm

IBM/GF/Samsung 28nm metal pitch - 90nm
IBM/GF/Samsung 20nm metal pitch - 64nm
IBM/GF/Samsung 14nm metal pitch - 64nm

TSMC 28nm metal pitch - 96nm
TSMC 20nm metal pitch - 64nm
TSMC 16nm metal pitch - 64nm

*** 1D/2D routing ***

Intel 32nm routing - 1D
Intel 22nm routing - 1D
Intel 14nm routing - 2D

IBM/GF/Samsung 28nm routing - 2D
IBM/GF/Samsung 20nm routing - 2D
IBM/GF/Samsung 14nm routing - 2D

TSMC 28nm routing - 2D
TSMC 20nm routing - 2D
TSMC 14nm routing - 2D

If you follow the details of Intel's process implementation throughout the years you will notice that they have gone to much more restricted design rules in order to maintain their two year cadence. This is why I have included the routing of the interconnect, the pin to pin connections of the transistors. Clearly, unidimensional (1D) routing is easier to etch than 2D, and this has everything to do with restricted design rules.

Now, the problem is that you make it sound as if that the foundries have to "bite the bullet" on their 20 nm node whereas Intel does not have to. Which is not true.

Mark Bohr, the Senior Intel Fellow, went on record during IDF 2012:

The next generation 14 nm we're going to have to convert to Double Patterning to get tighter pitches.

So, at their 14 nm node Intel will have second generation FinFET architecture, and will have to convert to double pattering and use 2D routing.

In terms of PPA (Power, Performance, and Area), the foundries will not enjoy any density improvements since they will continue to use a 64 nm interconnect. However, they should have power and area improvement since they will move to the FinFET architecture.

Last, but far from the least, triple-patterning technology (TPT) is a strong option for handling the local metal layers of the upcoming 10 nm logic technology node (∼ 44–48 nm minimum feature pitch) if extreme-UV (EUV) lithography is still not ready. TPT will be required because the smallest pitch that can be produced using DPT is 48 nm.

 

[AtenRa]

*** Metal Pitch ***

Intel 32nm metal pitch - 113nm
Intel 22nm metal pitch - 90nm
Intel 14nm metal pitch - 64nm

IBM/GF/Samsung 28nm metal pitch - 90nm
IBM/GF/Samsung 20nm metal pitch - 64nm
IBM/GF/Samsung 14nm metal pitch - 64nm

TSMC 28nm metal pitch - 96nm
TSMC 20nm metal pitch - 64nm
TSMC 16nm metal pitch - 64nm

Are you sure that GF 28nm metal pitch is at 90nm ?? Maybe im wrong but metal pitch of GF 28nm is at 114nm. 80nm is for the 20nm process.

Also, TSMC metal pitch of 28nm process is at 120nm.

 

[carop]

Are you sure that GF 28nm metal pitch is at 90nm ?? Maybe im wrong but metal pitch of GF 28nm is at 114nm. 80nm is for the 20nm process.

Also, TSMC metal pitch of 28nm process is at 120nm.

You seem to have the incorrect numbers.

The numbers for IBM/GF/Samsung are from Paul McLellan at SemiWiki who took a spy shot at an IBM event:

http://www.semiwiki.com/forum/content/1780-ibm-tapes-out-14nm-arm-processor-cadence-flow.html

The numbers for TSMC are from Hans de Vries at the Chip Architect, and UBM TechInsights:

http://www.chip-architect.com/news/2010_09_04_AMDs_Bobcat_versus_Intels_Atom.html

http://www.ubmtechinsights.com/uploadedfiles/sample_dsa_logic.pdf


However, the numbers you quote seem to match the Contacted Gate Pitch.

*** Contacted Gate Pitch ***

Intel 32nm contacted gate pitch - 112nm
Intel 22nm contacted gate pitch - 90nm (80nm with special processing)
Intel 14nm contacted gate pitch - unknown

IBM/GF/Samsung 28nm contacted gate pitch - 114nm
IBM/GF/Samsung 20nm contacted gate pitch - 90nm
IBM/GF/Samsung 14nm contacted gate pitch - 80nm

TSMC 28nm contacted gate pitch - 118nm
TSMC 20nm contacted gate pitch - unknown
TSMC 14nm contacted gate pitch - unknown

 

[AtenRa]

Hmm, yea those are for contacted gate pitch my bad

 

[Idontcare]

I am talking about the metal interconnect.

The local metallization layers of logic products are historically the densest layouts to lithographically pattern and are key drivers of product density (and therefore cost).

Well that is the difference then. I was talking about sram (because that is what I was asked about), which is critically dependent on gate pitch.

Metal pitch matters too, but not if you can't get your gate pitch small enough. And that is where you need double-patterning to make the densest sram cells.

Now, the problem is that you make it sound as if that the foundries have to "bite the bullet" on their 20 nm node whereas Intel does not have to. Which is not true.

Not sure where you got the part in bold, of course Intel has to, but it is already baked into their existing scaling profile because they bit the bullet and adopted it for enabling aggressive gate pitch on previous nodes.

Once you cross the bridge you can't go back, so Intel has been relying on it now for multiple nodes. TSMC will get a nice one-time density boost (breaking with the node-on-node extrapolation curve), thereafter it will be necessary to keep doing it in order for them to stay on the curve (same as Intel).

It is no different than any other process-based enabler like HKMG or stress engineering. Once you cross the bridge and start doing it you do get an immediate one-time bump in key electrical parameters that break with expectation based on the dimensional scaling of traditional materials. But you can't go back, to remain on a traditional scaling path you must forever continue to rely on those innovations going forward.

That is why Intel's Finfets are also HKMG finfets which also happened to have the channels stressed to heck and back.

However, the numbers you quote seem to match the Contacted Gate Pitch.

*** Contacted Gate Pitch ***

Intel 32nm contacted gate pitch - 112nm
Intel 22nm contacted gate pitch - 90nm (80nm with special processing)
Intel 14nm contacted gate pitch - unknown

IBM/GF/Samsung 28nm contacted gate pitch - 114nm
IBM/GF/Samsung 20nm contacted gate pitch - 90nm
IBM/GF/Samsung 14nm contacted gate pitch - 80nm

TSMC 28nm contacted gate pitch - 118nm
TSMC 20nm contacted gate pitch - unknown
TSMC 14nm contacted gate pitch - unknown

If you want to make dense sram then you have no choice but to talk about contacted gate pitch. It is why people care about it enough to bother publishing the numbers (or not publish them if they fear it will do more harm than good to their brand).

 

[Ajay]

Not really sure what it means for AMD.

This article from April -> http://semimd.com/blog/2013/04/18/moving-on-two-fronts/

This video from May -> http://youtu.be/K6D39QqJWSU

 

[SocketF]

.
Go up 1 level on the link I provided
http://www.globalfoundries.com/technology/leading_edge_tech.aspx

... Our 28nm technologies are based on industry-standard bulk silicon substrates and utilize the same HKMG gate stack as our 32nm-SHP. The 28nm High Performance Plus (HPP) and Super Low Power (SLP) technologies are designed for a wide variety of applications from high-performance graphics and wired networking to low-power wireless mobile applications that require long battery lifetime....

Do you have any clue how old that information is
The following one however, is from February 2013:

Now we can discuss the semantics of "SHP" if it means SOI or not SOI, you can take the part and belief some kind of super-hyper-bulk process I believe in the SOI, because any SHP process used SOI up to now.

http://www.globalfoundries.com/technology/pdf/GF-14XM-Press-FINAL.pdf
Refer Page 6 & Page 7

For which purpose? What do you want to proof? You quote a long text with lots of different points.

But in Dec 2012 WSA the "Standard " nomenclature came to the picture. So it has been clear all along that FD-SOI is no go for AMD at 28nm.

Yes, I agree, as I wrote previously, I see FDSOI as an option at 20nm not at 28nm. You probably missed that.

Just a note FD-SOI 28nm is proprietary to ST Microelectronics and is home grown. So eventhough STM is a part of IBM consortium, it owns this and has the rights to the process.

You didnt hear about the fact that STM gave it to GF in exchange for its manufacturing capacity so everybody interested in it can use it? 28nm is somehow limited though, but 20nm (14nm) is open to everybody:

Chery said that with technology transfer agreements it was quite normal to have defined periods when the provider of the technology would continue to enjoy an advantage in the market. "We have been able to define a list of people at 28-nm who can have access to this technology," Chery told EE Times. When asked who would not be able to have access to 28-nm FDSOI, Chery said: "Not guys who compete [with ST] in chips for set-top box, home gateways and digital ASICs for networking." Chery declined to confirm or deny that Broadcom was a company that would not be given access to 28-nm FDSOI. "At the 14-nm node, the platform is completely open," Chery said.

http://www.eetimes.com/electronics-news/4414703/ST-to-deny-rivals-FDSOI-access

 

[galego]

Steamroller FX arriving in H2 2014?

Have you some link for that, please?

 

[chernobog]

I have done my research and information's in this thread were also useful.

It seems "Steamroller" will crush Haswell.

@galego

AMD's server roadmap and readiness for mass production of GF's foundries points just that, it seems AMD is planning to get head to head against Haswell refresh.

 

[Ajay]

I have done my research and information's in this thread were also useful.

It seems "Steamroller" will crush Haswell.

@galego

AMD's server roadmap and readiness for mass production of GF's foundries points just that, it seems AMD is planning to get head to head against Haswell refresh.

How on earth did you come up with that after reading this thread. It is possible that XV may have come close to Haswell (on performance). Though if XV comes out, it will be late, because 20nm @ GFL is late. SR *may* have had **some** of the features planned for XV added to it (we aren't even sure yet). Thus SR<XV<HW. The only math that can change this is imaginary. Geez, someone else to add to my ignore list, and it was just starting to shorten up.

 

[Sable]

How on earth did you come up with that after reading this thread. It is possible that XV may have come close to Haswell (on performance). Though if XV comes out, it will be late, because 20nm @ GFL is late. SR *may* have had **some** of the features planned for XV added to it (we aren't even sure yet). Thus SR<XV<HW. The only math that can change this is imaginary. Geez, someone else to add to my ignore list, and it was just starting to shorten up.

No no, he did scientific calculations.

http://forums.anandtech.com/showthread.php?t=2328076

 

[NostaSeronx]

Now we can discuss the semantics of "SHP" if it means SOI or not SOI, you can take the part and belief some kind of super-hyper-bulk process I believe in the SOI, because any SHP process used SOI up to now.

SHP always has some form of SOI included, whether it is SOS(really old), SOI(Includes FD-SOI, 90-nm -> 32-nm), or SOIFFETs(This one is dated for 20/14/11 -nm nodes).

No no, he did scientific calculations.

Kaveri 4C @ 2.6 GHz -> I put it at ~5.3(5.1 to 5.4) pts for R11.5.
8C Steamroller @ 2.0 GHz -> I would put it at ~9(8.6 to 9.3) pts for R11.5.

 

[chernobog]

No no, he did scientific calculations.

http://forums.anandtech.com/showthread.php?t=2328076

Simple calculation... I read couple of articles involving Steamroller and this is just an estimation of Steamrollers performance.

8 core steamroller will beat i7 4770k

6 core steamroller will beat i5 4670k and be close to i7 4770k

4 core steamroller will beat i3 4xxx and be close to i5 4760k

 

[galego]

Simple calculation... I read couple of articles involving Steamroller and this is just an estimation of Steamrollers performance.

8 core steamroller will beat i7 4770k

6 core steamroller will beat i5 4670k and be close to i7 4770k

4 core steamroller will beat i3 4xxx and be close to i5 4760k

Your estimations are based in Intel-only optimized benchmarks such as Cinebench. Steamroller will be faster with neutral benchs (i.e. optimized for both Intel and AMD).

Under neutral benchs a Piledrived 8350 already competes with Haswell 4770k and in some cases the 8350 even beats a six-core extreme 3960X.

 

[Sheep221]

Your estimations are based in Intel-only optimized benchmarks such as Cinebench. Steamroller will be faster with neutral benchs (i.e. optimized for both Intel and AMD).

Under neutral benchs a Piledrived 8350 already competes with Haswell 4770k and in some cases the 8350 even beats a six-core extreme 3960X.

Please provide link to your source(other than yourself), because in reality FX-8350 is nowhere near 3960X, 4670K or 3570K, and we yet skipped 3770 and 4770K.
And also explain how cinebench is "Intel-only opimized" and explain which benchmarks are "neutral".

 

[toyota]

the future is AMD. that is why galego does not have a pc now.

Personal attacks are not acceptable
-ViRGE