Not sure where you are going with all that but Intel already adopted double-patterning way back
in the time of 65nm and 45nm.
I am talking about the metal interconnect.
The local metallization layers of logic products are historically the densest layouts to lithographically pattern and are key drivers of product density (and therefore cost).
Due to delays in extreme-UV (EUV) lithography the foundries are using DPT (double-patterning technology) at their 20 nm node because the smallest pitch that can be produced using 193 nm immersion lithography is 80 nm.
The foundries and Intel have been using different metal pitch sizes up until the 14 nm node. Here are the details for your reference:
*** Metal Pitch ***
Intel 32nm metal pitch - 113nm
Intel 22nm metal pitch - 90nm
Intel 14nm metal pitch - 64nm
IBM/GF/Samsung 28nm metal pitch - 90nm
IBM/GF/Samsung 20nm metal pitch - 64nm
IBM/GF/Samsung 14nm metal pitch - 64nm
TSMC 28nm metal pitch - 96nm
TSMC 20nm metal pitch - 64nm
TSMC 16nm metal pitch - 64nm
*** 1D/2D routing ***
Intel 32nm routing - 1D
Intel 22nm routing - 1D
Intel 14nm routing - 2D
IBM/GF/Samsung 28nm routing - 2D
IBM/GF/Samsung 20nm routing - 2D
IBM/GF/Samsung 14nm routing - 2D
TSMC 28nm routing - 2D
TSMC 20nm routing - 2D
TSMC 14nm routing - 2D
If you follow the details of Intel's process implementation throughout the years you will notice that they have gone to much more restricted design rules in order to maintain their two year cadence. This is why I have included the routing of the interconnect, the pin to pin connections of the transistors. Clearly, unidimensional (1D) routing is easier to etch than 2D, and this has everything to do with restricted design rules.
Now, the problem is that you make it sound as if that the foundries have to "bite the bullet" on their 20 nm node whereas Intel does not have to. Which is not true.
Mark Bohr, the Senior Intel Fellow, went on record during IDF 2012:
The next generation 14 nm we're going to have to convert to Double Patterning to get tighter pitches.
So, at their 14 nm node Intel will have second generation FinFET architecture, and will have to convert to double pattering and use 2D routing.
In terms of PPA (Power, Performance, and Area), the foundries will not enjoy any density improvements since they will continue to use a 64 nm interconnect. However, they should have power and area improvement since they will move to the FinFET architecture.
Last, but far from the least, triple-patterning technology (TPT) is a strong option for handling the local metal layers of the upcoming 10 nm logic technology node (∼ 4448 nm minimum feature pitch) if extreme-UV (EUV) lithography is still not ready. TPT will be required because the smallest pitch that can be produced using DPT is 48 nm.