First Steamroller processor core exposure

[krumme]

How does size relate to complexity and the ressources needed for design?

I mean if bobcat was a quarter the size of k8 did it then use half, the double, 4, 16...the ressources to design. Under the asumption of taking the same liberties?

Saying if you have a small core a company like amd have perhaps different design opportunities than creating a larger core.

 

[Abwx]

A Bobcat core , and even more a Jaguar , is as big as a K8 core,
but it sure didnt require as much direct man hours than previous
uarch as it used as much as possible of existent sub blocks libraries ,
not counting that they had new tools at their disposal among others
efficient layout routing automation that reduce dramaticaly the otherwise
needed workforce.

 

[krumme]

A Bobcat core , and even more a Jaguar , is as big as a K8 core,
but it sure didnt require as much direct man hours than previous
uarch as it used as much as possible of existent sub blocks libraries ,
not counting that they had new tools at their disposal among others
efficient layout routing automation that reduce dramaticaly the otherwise
needed workforce.

As i remember bobcat with l1 was 4.6mm2 on 40nm, llano 9.6mm2 on 32nm. Now the 40nm was quite dense and using new lithography equipment, but i dont think its far off to describe bobcat as at least less than half size.

 

[Abwx]

Llano is not K8 , it s K10.5 , slightly bigger than Phenom II core, ie K10.
K8 is either Athlon 64 single or dual core only.

 

[krumme]

Llano is not K8 , it s K10.5 , slightly bigger than Phenom II core, ie K10.
K8 is either Athlon 64 single or dual core only.

You are right i missed the k8 , but where do you derive the numbers from to assume they are the same size?

 

[Abwx]

You are right i missed the k8 , but where do you derive the numbers from to assume they are the same size?

The die below is 199mm2 , the two cores account
for 25% at most , that s about 25mm2 per core at 90nm ,
at 45nm it woud be 6mm2 , 4.7mm2 at 40nm and 2.35mm2
at 28nm , wich is smaller than Jaguar but still bigger than Bobcat.

http://www.pcper.com/reviews/Processors/AMD-Athlon-64-X2-4400-Dual-Core-Processor-Review

 

[CTho9305]

Bobcat's ALUs and vALUs are from 00h/K8. The cache structure, front-end structure, back-end structure is mostly taken from Bulldozer.
Jaguar's ALUs and vALUs are from 10h/K10. The cache structure, front-end structure, back-end structure is mostly taken from Steamroller.

Certain aspects of Bobcat/Jaguar make them more superior than 00h/10h/11h/12h/15h. Generally, they are better with CISC and the latency involved with CISC.

Do you just make this stuff up? I've seen posts where you state things as fact that I know are completely wrong, and occasionally bits of accurate information are sprinkled in... but you state them all as if they're verified fact. And you never cite sources. It's incredibly annoying.

How does size relate to complexity and the ressources needed for design?

I mean if bobcat was a quarter the size of k8 did it then use half, the double, 4, 16...the ressources to design. Under the asumption of taking the same liberties?

Saying if you have a small core a company like amd have perhaps different design opportunities than creating a larger core.

While size and complexity are related, they're not always as well-correlated as you might expect. You can make a big core just with large caches (the K7 family had 64KB+64KB L1's) and large structures (deep scheduler queues, etc), without a lot of complexity (for example, older microarchitectures in the K7/K8 family executed loads and stores mostly in-order; Bobcat can reorder more of them, which adds a lot of complexity even if it takes less space).

As for resources required to do a design, you do get some "standing on the shoulders of giants" effects, so a particular level of complexity does become easier to design over time.

 

[NTMBK]

Do you just make this stuff up? I've seen posts where you state things as fact that I know are completely wrong, and occasionally bits of accurate information are sprinkled in... but you state them all as if they're verified fact. And you never cite sources. It's incredibly annoying.

Some of it is interesting speculation- and speculation is no bad thing- but it is never labelled as such.

 

[NostaSeronx]

Do you just make this stuff up?

No. My posts are backed with some facts and some hints.

And you never cite sources.

If you uploaded a valuable amount of private information to the internet(whether it private or protected). Not realizing how resourceful the internet is would you like to lose your job? I will only source if there is no plausible NDA because I am not a jerk. The other rule is that I have a pdf or powerpoint because they are usually from who ever builds what I am looking for.

Just for example: There was a lot of leaked Jaguar slides, powerpoints, and txt files detailing performance.

 

[parvadomus]

The die below is 199mm2 , the two cores account
for 25% at most , that s about 25mm2 per core at 90nm ,
at 45nm it woud be 6mm2 , 4.7mm2 at 40nm and 2.35mm2
at 28nm , wich is smaller than Jaguar but still bigger than Bobcat.

http://www.pcper.com/reviews/Processors/AMD-Athlon-64-X2-4400-Dual-Core-Processor-Review

The K8 was an amazing piece of silicon. It has one of the best performances per mm2. Maybe better than intel core series?

 

[Idontcare]

No. My posts are backed with some facts and some hints.If you uploaded a valuable amount of private information to the internet(whether it private or protected). Not realizing how resourceful the internet is would you like to lose your job? I will only source if there is no plausible NDA because I am not a jerk. The other rule is that I have a pdf or powerpoint because they are usually from who ever builds what I am looking for.

Just for example: There was a lot of leaked Jaguar slides, powerpoints, and txt files detailing performance.

The problem here NostaSeronx is that we have members in this forum who directly worked on the Bobcat processor (not in marketing, not in sales, but directly worked on it as design engineers) and they are telling me you are 100% dead wrong.

Now these are people I know and have interacted with in real life. So when they say this to me (and who would know better than the bobcat engineers themselves?) it really tells me that you are just making up crap and trying to spin it as "from insiders who must remain secret".

On the off-chance you really are just passing along BS info (and it IS BS info) that has been passed to you, making you the hapless goon in the info-fail chain, then you should take this feedback as a wake-up call to stop allowing yourself to be used as a mouthpiece for seeding the forums with known-BS info about AMD products.

If, however, you are just doing this because you like to "roll like a troll" then I have no doubt you tell me I am wrong (which will raise cackles among a few engineers here) and persist in posting more BS info posts in the forums.

The nice thing about a binary logic decision tree is all we have to do is sit back and let you make your next move, thus proving to us which side of that fence you have been sitting on until now.

That you are spreading false information is without question, whether you are doing it unwittingly or knowingly is the question and your future posts will tell us precisely which is the case

Your move.

 

[PPB]

And the part where you refute his statements with actual technical information...? Or is it one of those "you have to trust me on this" kind of posts?


In any case, it is just as his affirmations without actual proof

 

[Abwx]

The K8 was an amazing piece of silicon. It has one of the best performances per mm2. Maybe better than intel core series?

Older uarch had indeed better perfs/mm2 since increasing
the transistor count by say 2 will only yield better perfs
in the 20% or 30% at best if everything is optimised
for the new uarch.

 

[Exophase]

And the part where you refute his statements with actual technical information...? Or is it one of those "you have to trust me on this" kind of posts?


In any case, it is just as his affirmations without actual proof

No need to take anyone's word for it, AMD has publicly released a very generous amount of documentation on Bobcat and especially Jaguar, and at least a reasonable amount for Bulldozer and Piledriver. There's also sources like GCC you can glean uarch info from..

Saying that BD and Bobcat share the same vector units is just profoundly inaccurate. Off the top of my head:

- Bobcat has two execution ports, Bulldozer has four
- Bobcat has only 64-bit FP and integer execution, Bulldozer has 128-bit
- Bobcat has FADD and FMUL pipes, Bulldozer has two FMA pipes
- Bobcat has 2-3 cycle latency FP operations, Bulldozer is 5-6 cycles (this means a really fundamentally different approach in how the pipeline is designed)
- Bobcat only supports up to SSSE3, while Bulldozer supports SSE4.x, AVX, FMA, and XOP and has the real execution to back it
- AFAIK Bobcat doesn't have SIMD move elimination, while Bulldozer does

Jaguar mainly changes things by widening the units to 128-bit, adding SSE4.x and AVX, tightening some timings and I think removing some microcodings. I'm not aware of any changes Piledriver makes to the vector part at all.

This is all backed by easily available documentation: look at slides, publications from HotChips, optimization guides, Agner Fog's manuals, GCC scheduler definitions, and so on..

Probably NostaSeronx saw something that he thinks says what he does but actually says something completely different (although how anyone could misconstrue somethnig into this is a real headscratcher), or he saw something that isn't actually from a reliable source.

 

[itsmydamnation]

there are also things on the "int side" like AGU's bobcat/jag have a dedicated load and a dedicated store AGU, bulldozer has two AGLU's and K8 has AGU's paired to ALU's.

I want AMD to do well but NostaSeronx is well into crackerjack land.

 

[NTMBK]

And the part where you refute his statements with actual technical information...? Or is it one of those "you have to trust me on this" kind of posts?


In any case, it is just as his affirmations without actual proof

IDC has a history of working in the industry (at TI) and has a long track record of being correct. Seronx has a long track record of just completely making shit up- I picked out a few nuggets in this post: http://forums.anandtech.com/showpost.php?p=35207303&postcount=212

 

[CTho9305]

And the part where you refute his statements with actual technical information...? Or is it one of those "you have to trust me on this" kind of posts?


In any case, it is just as his affirmations without actual proof

I actually respect my NDAs, so I usually can't give specific technical information. Fortunately, Exophase did a good job refuting the pure, unadulterated BS in the post I'd quoted.

 

[Phynaz]

And the part where you refute his statements with actual technical information...? Or is it one of those "you have to trust me on this" kind of posts?


In any case, it is just as his affirmations without actual proof

CTho9305 was a CPU designer for AMD until very recently.

Who would you think is correct?

 

[pelov]

IDC has a history of working in the industry (at TI) and has a long track record of being correct. Seronx has a long track record of just completely making shit up- I picked out a few nuggets in this post: http://forums.anandtech.com/showpost.php?p=35207303&postcount=212

What I find to be the most amusing are the talks of 'first' and 'second' version of Steamroller. AMD released a lot of technical info that directly contradicts a lot of these baseless rumors, so the fallback is to claim that was just the 'first' version of the Steamroller uArch. Apparently, less than a year is enough to completely rework the architecture, make a new mask, produce an engineering sample and go through all of the validation steps required to see a product through to its release.

 

[galego]

What I find to be the most amusing are the talks of 'first' and 'second' version of Steamroller. AMD released a lot of technical info that directly contradicts a lot of these baseless rumors, so the fallback is to claim that was just the 'first' version of the Steamroller uArch. Apparently, less than a year is enough to completely rework the architecture, make a new mask, produce an engineering sample and go through all of the validation steps required to see a product through to its release.

We heard rumours about a Steamroller "A" and Steamroller "B". Hot chips 2012 and its 20-30% IPC seems to be about "A", but recent interview made to Feldman the last month and its claims that Steamroller core has 2x the performance of the Jaguar core seems to be about "B".

It seems that eight core Steamroller FX line and 6C Kaveri were part of the plans for Steamroller "A", whereas the recent roadmaps, where eight core Steamroller FX and 6C Kaveri do not appear, and where 8C piledriver are substituted by 4C Steamroller are the plans for Steamroller "B".

 

[pelov]

That doesn't explain why you and others believe that less than a year is enough to revise the core architecture...

Steamroller A might just be an engineering sample where Steamroller B might be a newer engineering sample. Why you or anybody else believe that AMD heavily revised their uArch in less than a year is the question here.

 

[NTMBK]

We heard rumours about a Steamroller "A" and Steamroller "B". Hot chips 2012 and its 20-30% IPC seems to be about "A", but recent interview made to Feldman the last month and its claims that Steamroller core has 2x the performance of the Jaguar core seems to be about "B".

It seems that eight core Steamroller FX line and 6C Kaveri were part of the plans for Steamroller "A", whereas the recent roadmaps, where eight core Steamroller FX and 6C Kaveri do not appear, and where 8C piledriver are substituted by 4C Steamroller are the plans for Steamroller "A".

Here's an alternative hypothesis:

-Hot Chips 2012 was talking about Steamroller
-Steamroller has 2x the performance of the Jaguar core
-There was never any 8 core or 6 core Steamroller, and the 4 core Kaveri was the plan from the start
-There is no Steamroller "a" and "b"

See this roadmap from April 2012 article (http://news.softpedia.com/news/AMD-...-Bring-Significant-Performance-264918.shtml)?

This was 4 months before Hot Chips 2012. The part they talked at at HC2012 was the same part on these roadmaps- the 4 core APU, with no 8 core CPU counterpart and no 6 core APU. There was no "A" and "B".

 

[Exophase]

We heard rumours about a Steamroller "A" and Steamroller "B". Hot chips 2012 and its 20-30% IPC seems to be about "A", but recent interview made to Feldman the last month and its claims that Steamroller core has 2x the performance of the Jaguar core seems to be about "B".

Did you forget that Kyoto only clocks at up to 2GHz, just like every other Jaguar part we currently know of?

Berlin will clock at as much as twice that. That alone would account for a 2x performance difference, probably higher.

 

[PPB]

CTho9305 was a CPU designer for AMD until very recently.

Who would you think is correct?

I believe whoever has the most solid point. And that involves avoiding childish falacies like this one i quoted. I dont say he didnt work at AMD, just if that is enough to avoid refuting an affirmation with actual information. We have good examples of people involved in chip design and that didnt stop them from spreading false information (intel ama guy and haswells supposed excelence at overclocking comes to mind).

Exophase just showed you can do it the way i described without compromising ndas, etc

 

[Keysplayr]

And did Exophase have the most solid point, according to whatever metrics you use to gauge?
We all know CTho was a cpu designer for AMD. We have established that he knows his stuff.
We've also established that we don't know you at all.
And calling what you qoted a childish fallacy is now giving us an idea though.