Found another one: Ukraine store accidentally ships FX-8120 and it gets tested!

Page 10 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
Actually FLOP is both singular and plural

In that case it was a plural , but anyway , the reference to
floating point operation per second is really irrelevant since
the numbers in discussion are obviously about Flops/cycle....
 

jones377

Senior member
May 2, 2004
451
47
91
No, I am a unicorn in a mystical land of fairies

Yes, I thought so. Anyways, you're still wrong but I'm done with you. Enjoy your ignorance. Don't let anyone ever teach you anything, you know everything you'll ever need to know.

plonk
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,689
1,224
136
Yes, I thought so. Anyways, you're still wrong but I'm done with you. Enjoy your ignorance. Don't let anyone ever teach you anything, you know everything you'll ever need to know.

plonk


(8 32bit Ops, 4 (2x32bit)64bit Ops) * 8 Units * 3.4GHz
8 * 8 = 64 Flop

64 Flop * 3.4GHz = 217.6 GFlops

You're still wrong, a SB core can do 2*256bit AVX FP per cycle.

I am saying you are correct it does do 2*256bit AVX FP per cycle

8 x 32bits = 256bits
4 x 64bits = 256bits

8 Units that can do 256bits

in i7 2600K(2 units per core)

but after that Abwx explains more v
 
Last edited:

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
Are you for real?

He s half right at least...

SB ports are not universal , meaning that one port make
FADDs while the other exe port will do FMULs..

If only FADDs or only FMULs are dispatched , only one
port will be active , halving the thoughput.
In contrast , the two Fmac units in a BD FPU can both
do both operations, so throughput will remain constant if
only a kind of op is dispatched..
 

jones377

Senior member
May 2, 2004
451
47
91
He s half right at least...

SB ports are not universal , meaning that one port make
FADDs while the other exe port will do FMULs..

If only FADDs or only FMULs are dispatched , only one
port will be active , halving the thoughput.
In contrast , the two Fmac units in a BD FPU can both
do both operations.

Yes I know this thx
 

bronxzv

Senior member
Jun 13, 2011
460
0
71
If only FADDs or only FMULs are dispatched , only one
port will be active , halving the thoughput.

with two running threads it's less likely to occur, you can have a series of VADDPS/D in one thread and a series of VMULPS/D in the other thread at a given moment for example and they will effectively use the 2 ports
 
Last edited:

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
with two running threads it's less likely to occur, you can have a series of VADDPs in one thread and a series of VMULPS in the other thread at a given moment for example

Thanks to the compiler that is aware than sending two simultaneous
FADD or FMUL in a same thread will be innefficient in respect of the Uarch , even if a computation would normaly require two same ops to be computed first due to data dependencies...

We ll see how softs are recompiled to take advantage
of BD FPUs....
 

bronxzv

Senior member
Jun 13, 2011
460
0
71
Thanks to the compiler that is aware than sending two simultaneous
FADD or FMUL in a same thread will be innefficient in respect of the Uarch , even if a computation would normaly require two same ops to be computed first due to data dependencies...

from my experience the scheduling at the code level has nearly no impact on Sandy Bridge, the Intel compiler generally schedule mixed VMULPx and VADDPx, the cases I was refering to where for typical use cases like a scaling loop with only MUL or an offset loop with only ADD
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
from my experience the scheduling at the code level has nearly no impact on Sandy Bridge, the Intel compiler generally schedule mixed VMULPx and VADDPx, the cases I was refering to where for typical use cases like a scaling loop with only MUL or an offset loop with only ADD

In that case , it s possible to do these ops
in two threads if there s no data dependencies ,
otherwise it would be too cycles consuming to dispatch
the two same ops in two cores and then retrieve the datas
to the completing core for further computations using these said datas...

hope i did explain accurately my thoughts...
 
Last edited:

bronxzv

Senior member
Jun 13, 2011
460
0
71
In that case , it s possible to do these ops
in two threads if there s no data dependencies ,
otherwise

yes, sure, the use cases I have in mind are with data decomposition, i.e. the two threads are working on two distinct datasets (appart some common read only data) and without synchronization

all the magic occurs at runtime thanks to the OOO engine and SMT
 

notty22

Diamond Member
Jan 1, 2010
3,375
0
0
o/t
Here is a good article from the past. Where AMD went with a dual FX cpu platform to compete with Intel's new (at the time) quad core.
That was interesting at the least.
Maximum PC - Feb 2007
 

RussianSensation

Elite Member
Sep 5, 2003
19,458
765
126
FX 4100 X4 8MB 3600MHZ Tray 95W - $120.68 (Provantage).

FX 6100 6C AM3 14MB 3300MHZ Tray 95W - $190.57

FX 8120 8C AM3 16MB 3100MHZ Tray 125W - $222.10

FX 8150 8C AM3 16MB 3600MHZ 125W Tray - $267.75

The same website sells X6 1090T for $179.87, X6 1100T for $206.24, i5-2500k for $220.10, i7-2600k for $323.72.

If true, 2500k will be going head-to-head vs. FX-8120, but based on the leaked benchmarks, it takes an 8150 just to keep up with the 1100T. Not sure how AMD intends to sell 8120 for $220 and 8150 for $266. Why would anyone buy the FX-4100 instead of a $119.99 Phenom II X4 955?? AMD's pricing is way too optimistic, unless those benchmarks are using 20% slower BIOS.
 
Last edited:
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |