I'm using a virtex 2 fpga and my input clock is only 12.5 MHz. I need both a 90 deg and 270 deg phase shifted clock to be generated internally and unfortunately I found out the DLL in the virtex is rated for a minimum input of 24 MHz to work correctly. I was able to bypass the software error by changing my 'listed' input frequency and output frequency to 25 mhz in order to keep a 1:1 ratio. I checked the output clocks and they seem to be fine and properly shifted. Is there anything I should be worried about?