Sorry to sway you guys here, but I need some help with my homework. I can't talk to the prof or the TA's because all of there office hours are during another class or when I am at work. I understand the big picture but some minor details have had me stumped for hours and I am starting to waste my time now.
I basicly need to design a FPU that adds two IEEE 754 32-bit numbers. The numbers are always positive so the sign bit will always be 0.
I understand the first step is to compare the exponents of both and shift the fraction of the smaller one the same number of places that the exponents differ.
Here is how I have done that...
VHDLish pseudocode
E1 is a register to hold the one exponent
E2 is a register to hold the second exponent.
F1 and F2 are the respective fractions in shift registers.
here is my algorithm
start :
if E1< E2 then
{
shift F1 right 1
E1 <= E1 + 1
goto start
}
elsif E2<E1 then
{
shift F2 right 1
E2 <= E2 + 1
goto start
}
else
{
SUM = F1 + F2
}
Now the first 1 in the before the fraction part is implied by the standard so do I load the fractions into a 24-bit register and load the 1 into the highest order bit? That way when I shift I don't have to do any combinational logic to figure out whether I put in a 1 or a 0 in the serial in.
As for the check for normalization, I just have to see if there is a 1 in the most significant bit right? The only way there wouldn't be a 1 is if I had to add 1.1 ... + 0.1 .... that would result in 10.0...
as you can see I am getting really confused. I have done tons of searching on the web and they explain the algorithm clearly but not much of the logic that goes behind it.
If don't think this is appropriate for this forum, please flame away and I will remove it
I basicly need to design a FPU that adds two IEEE 754 32-bit numbers. The numbers are always positive so the sign bit will always be 0.
I understand the first step is to compare the exponents of both and shift the fraction of the smaller one the same number of places that the exponents differ.
Here is how I have done that...
VHDLish pseudocode
E1 is a register to hold the one exponent
E2 is a register to hold the second exponent.
F1 and F2 are the respective fractions in shift registers.
here is my algorithm
start :
if E1< E2 then
{
shift F1 right 1
E1 <= E1 + 1
goto start
}
elsif E2<E1 then
{
shift F2 right 1
E2 <= E2 + 1
goto start
}
else
{
SUM = F1 + F2
}
Now the first 1 in the before the fraction part is implied by the standard so do I load the fractions into a 24-bit register and load the 1 into the highest order bit? That way when I shift I don't have to do any combinational logic to figure out whether I put in a 1 or a 0 in the serial in.
As for the check for normalization, I just have to see if there is a 1 in the most significant bit right? The only way there wouldn't be a 1 is if I had to add 1.1 ... + 0.1 .... that would result in 10.0...
as you can see I am getting really confused. I have done tons of searching on the web and they explain the algorithm clearly but not much of the logic that goes behind it.
If don't think this is appropriate for this forum, please flame away and I will remove it