Ah, marketing die shot like GM204's where all the actual drawn structures more or less resemble that of the logical diagram.
I have another interpretation of P10's marketing die shot:
GCN1 (Tahiti), GCN2 (Hawaii), GCN3 (Tonga/Fiji) CU diagrams are exactly the same. So this remains constant at the logical level across the four architecture revisions.
36CUs are shown. A GCN CU has 64SP in 4x16 groups, 16+4 units making up texturing hardware plus other necessary hardware. The differently colored 16u + 4u block has to be the texturing hardware.
16u green blocks * 4 = 64 SPs
16u yellow blocks = 16 TF/LS
4u green line next to yellow blocks = 4 TMUs
This forms a CU. The extra hardware depicted in the logical diagram has to be in these 16 large blocks in the outer regions and the smaller 4u lines in between CUs have the same color, these are probably registers, or L1 and L2 caches. Scalar unit, message unit, scheduler, etc, don't seem to be included.
ROPs, geometry processors, etc are decoupled from the CU and should be in the middle section of the diagram, probably. So should be ACE/HWS units. Memory controllers obviously in the periphery.
Going by this way of seeing it we have:
All this shows is the marketing die shot matches the high level diagram shown in the slides, nothing more. P10 at the physical level may very well have redundancy built in as any sanely designed chip should have (seen in the console APUs, 2-4 extra CUs thrown in there, disabled to guarantee yields), it may very well have extra hardware built in that's disabled at this time and may never be enabled (like Tonga's extra 128 bit memory controller chunk, Kaveri's memory controller GDDR5 support, etc), or it may very well be a design that's shipping 100% functional in what seem to be the truckloads, making GloFo a miracle foundry up from a disaster literally overnight with Samsung's help. Overvolted dies across the board, yes, but functional.
Silverforce has a point, quite a valid one in that one shouldn't believe any claims this early in the silicon's life over the specs. Especially with this slide floating around
RX485 could exist going by that. It's anyone's guess where they're going with that naming scheme.
edit: oh, I was late while making this post. Higher resolution marketing die shot confirms what I thought, more or less.
I have another interpretation of P10's marketing die shot:
GCN1 (Tahiti), GCN2 (Hawaii), GCN3 (Tonga/Fiji) CU diagrams are exactly the same. So this remains constant at the logical level across the four architecture revisions.
36CUs are shown. A GCN CU has 64SP in 4x16 groups, 16+4 units making up texturing hardware plus other necessary hardware. The differently colored 16u + 4u block has to be the texturing hardware.
16u green blocks * 4 = 64 SPs
16u yellow blocks = 16 TF/LS
4u green line next to yellow blocks = 4 TMUs
This forms a CU. The extra hardware depicted in the logical diagram has to be in these 16 large blocks in the outer regions and the smaller 4u lines in between CUs have the same color, these are probably registers, or L1 and L2 caches. Scalar unit, message unit, scheduler, etc, don't seem to be included.
ROPs, geometry processors, etc are decoupled from the CU and should be in the middle section of the diagram, probably. So should be ACE/HWS units. Memory controllers obviously in the periphery.
Going by this way of seeing it we have:
- 9 CUs per quadrant (36CUs total)
- 64SP*9=576SPs per quadrant and 2304 total
- 16TF/LS units per CU, 144 per quadrant, 576 total
- 4 TMUs per CU, 36 per quadrant, 144 total
All this shows is the marketing die shot matches the high level diagram shown in the slides, nothing more. P10 at the physical level may very well have redundancy built in as any sanely designed chip should have (seen in the console APUs, 2-4 extra CUs thrown in there, disabled to guarantee yields), it may very well have extra hardware built in that's disabled at this time and may never be enabled (like Tonga's extra 128 bit memory controller chunk, Kaveri's memory controller GDDR5 support, etc), or it may very well be a design that's shipping 100% functional in what seem to be the truckloads, making GloFo a miracle foundry up from a disaster literally overnight with Samsung's help. Overvolted dies across the board, yes, but functional.
Silverforce has a point, quite a valid one in that one shouldn't believe any claims this early in the silicon's life over the specs. Especially with this slide floating around
RX485 could exist going by that. It's anyone's guess where they're going with that naming scheme.
edit: oh, I was late while making this post. Higher resolution marketing die shot confirms what I thought, more or less.
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