Since when does ARM allow deep modification of its licensed cores?
I am always very skeptical when I see claims like this, because to the best of my knowledge, it has literally never happened.
I say probably because the RGCloudS guy on twitter has been saying Samsung is cooking some exotic ARM cores. Apparently they are going to use some special modified Cortex X5s in their 2025 Exynos 'Dream Chip'.
Indeed.Since when does ARM allow deep modification of its licensed cores?
I am always very skeptical when I see claims like this, because to the best of my knowledge, it has literally never happened.
But are they? Do we already have confirmations? I'm not sure I'd want to hold my breath already for actually seen multiple ARM based PC devices maybe beyond select QC devices.So now that so many players are jumping into the ARM PC bandwagon
Cardyak on twitter. I've found the block diagrams to be very accurate (see the link in the post below). There are block diagrams of a large variety of cores from AMD/Intel/Apple/ARM.
I remember reading for the first time Andrei's review of the A13 Bionic, as a 13 year old. It blew me away. How far we have come...I'm only a "average user", very ignorant that knows nothing about these things.
But after reading Anandtech in the beginning of the 2000's é now seeing CPU with 9-wide decode and 8 ALU... wow 😮
Wasn't Cortex X supposed to allow for much more custom design on top of the base ARM IP?The Built-on-Cortex program only allows for slight modifications.
Nvidia's strength is their excellent GPU IP, but other than that, do they have anything going for them?
Since when does ARM allow deep modification of its licensed cores?
Not surprising whatsoever. Arm designs for low power + performance, but they can only go so far with the area constraints at hand.Crazy a15 is still better in performance and energy efficiency.. so the x5 core will reach a16 while apple a19 will increase the lead
Yeah firestorm is a impressive core in ppwNot surprising whatsoever. Arm designs for low power + performance, but they can only go so far with the area constraints at hand.
The X4 is a generic Firestorm core. Matches an M1/A15 roughly on GB5 and close on Spec, albeit 26% more power draw (in the Spec example and probably similar for GB5 with the 8 Gen 3).
In a laptop SoC on the same process, I'd bet this thing would still draw less power than e.g. Phoenix would at that performance, and certainly they have a good 25% ish perf/GHz lead on AMD.
But it's not going to close a gap with Apple or Qualcomm without more cache and probably a different cache hierarchy with respect to the L1, which might be what they'll change with the next core. They'll have to keep growing it a bit to keep pace.
Qualcomm did go with 2MB of L2 on the X4 per Geekkwan's review btw, which is good - doesn't seem like that's restricted to a datacenter thing at all. Lot of predictions look silly now on that end.
If by "the space" you mean SoC's purely for WoA laptops and NUC/Mac Mini style desktops then it's not really entering for either of them.Which puts Nvidia and AMD in a weird position if they are also entering the space themselves (!?).
Uh, Cortex. Neoverse is for servers. It won't be custom either IMHO. It's possible they'll do a MediaTek co-packaged Windows solution but based on the rumor about the Surface contract and what Qualcomm lost, I think it's probably likely Nvidia has a real laptop SoC with Cortex reference cores and a low power adaptation of new GPU IP on something like N3E for 2025.If by "the space" you mean SoC's purely for WoA laptops and NUC/Mac Mini style desktops then it's not really entering for either of them.
On AMD's side their APUs are basically doing that already just on a different CPU ISA.
While nVidia has been milling about with Tegra for over a decade already, so it's just a matter of software platform migration in their case.
The only question is will nVidia's effort be based on Cortex or Neoverse IP given the last Tegra chip (Orin?) was based on A78, and Grace is based on V2.
There's nothing intrinsically stopping an SoC designer from using Neoverse IP for consumer uses, though I imagine that licensing Neoverse is more expensive as generally server stuff is more profitable.Uh, Cortex. Neoverse is for servers
That's a given.It won't be custom either IMHO
Huh, really? Iso node too?The X4 is a generic Firestorm core. Matches an M1/A15 roughly on GB5 and close on Spec, albeit 26% more power draw (in the Spec example and probably similar for GB5 with the 8 Gen 3).
N4P. But not that much of a gap between it and the N5P the A15 was on, and it draws about 26% more power (5.7W vs 4.5W) for Spec by trailing by about 8-10%. That’s still really, really good for the area & cache Arm are working with. GB5 it’s about 1693 @ 3.3GHz and probably similar power. Check the latest Geekerkwan video.Huh, really? Iso node too?
It wouldn’t make much sense. Sure in principle but why? They have extra area penalties and are built for different workloads and are usually lagging the real Cortex cores. They’d sooner just do X5 + smaller X5, Arm is flexible deliberately.There's nothing intrinsically stopping an SoC designer from using Neoverse IP for consumer uses, though I imagine that licensing Neoverse is more expensive as generally server stuff is more profitable.
That's a given.
nVidia tried custom with Denver 1/2 and Carmel, but ultimately they couldn't match (let alone surpass) ARM's own designs well enough for the R&D cost to be worth it.
Same thing with Qualcomm's OG Kryo.
Even worse with Samsung's Mongoose3/M3/Meerkat.
A 6 wide µArch getting curb stomped by a 4 wide µArch (A76+) is not a good look.
It truly just goes to show how good the ARM Ltd design teams are to be able to compete with such comparatively huge companies.
Lower clock yes, smaller unlikely.They’d sooner just do X5 + smaller X5
Nah the X4’s smaller version is 1/2-1/4 the L2 and has amaller SIMD units (2X128B like the A720) which is huge in reducing the overall area but you’d still get better performance than the A720’s. I absolutely could see them doing a 4+4 design of that kind. Lower clock is just the other part of it. Much like MediaTek’s 9300 but adapted for a PC and replace the A720’s with the smaller X cores, make the first four all big.Lower clock yes, smaller unlikely.
Xn are designed with raw perf in mind over area and power vs the PPA balance of A7x/7xx.
When you already have a good balance it's easier to trade off something in the design to get a bit more area or power as ARM offers with the A720 lite variant.
I'm pretty confident now that X5/Blackhawk will be the basis for V3/Poseidon - that's why I was thinking a V3 based hi end WoA SoC might be possible being as the Grace successor will almost certainly be using it anyway.
Very unlikely I know, but still a possibility - and to me a better choice as we still lack for a System Ready type of spec for Cortex based SoCs.
(unless I missed a PR slide SDXE is not System Ready either?)
No.Don't ARM cores face this conundrum?
Samsung already uses AMD's RDNA GPU IP in their Exynos Mobile SoCs.
No.
On older ARM gens, all the cores have at least barebones support for NEON instructions. On newer ARM versions you have SVE2 which (long story short) can be supported on all compliant ARM cores regardless of vector width for that specific core.
Note that anything ARMv8.x it's pretty much just NEON or in-house instruction sets.
That's interesting. Unsafe how? Are we talking execution failure or security issues?namely, process migration to a core with a different vector length during a vectorized loop body is unsafe.
That's interesting. Unsafe how? Are we talking execution failure or security issues?
So since they don't exist, I haven't tested any of this on a real vector-width-heterogeneous machine - I've only ever worked with SVE1 and only on server-class silicon. But my thinking is that if you have a migration midway through an SVE iteration - at least, a after any vector op that affects state (so, reduction ops, vector stores) based on the lanes only available in the bigger core - onto a narrower vector length, you're likely to have problems of the "your program no longer works correctly" variety. With any luck, it would just see that the generated predicate is out of range and crash, rather than continuing on an Undefined Behavior Adventure.
It's been a minute, so I'll look at the docs later and see if ARM comments on this particular scenario.