Ok, I'm not super hardware guy, I'm a software engineer by trade. But I did take computer architecture in school and liked it, I get piplining and scoreboarding and basic ISA stuff. So please be gentle, I'm wondering if some chip people that frequnet here care to stretch their imaginations with me.
It seems that x86 is here to stay, at least for another decade is mass numbers, probably much longer than that. We all know that the newer pentiums actually translate x86 instructions into RISC-like instructions, and the core of the processing is done in a much more RISC-like manner.
With the new growing trend toward massive on-die integration (dual cores, memory controllers, etc) I'm wondering if some itanium style-architectures could be used on a chip that translates x86 to EPIC type instructions. With all the space used for mupltiple cores, memory controllers, crypto units, and other goodies that future integration will bring, it doesn't seem to hard to throw in a buttload of extra registers for EPIC-style instructions. Bear in mind that my knowledge of EPIC is very limited, basically "use a buttload of registers and accomplish more tasks in parallel," is all I know.
I'm thinking potentially we could have a bunch of shared registers between multiple cores, this may improve paralellism or do some EPIC-like things. It may lead to a bigger hyperthreading technology, like ultra-threading or something.
I'm just thinking that a lot of the ideas used in EPIC seem potentially compatible with future chip designs, now that we have abandoned the Mhz push and are going to be looking for more powerful chips through integration and features. Anyone have any ideas of the possibilites that are clearer than my lack of expertise? I'm just a dreamer here, I don't wanna hear "that's impossible" replies. This is just high-level dreaming.
It seems that x86 is here to stay, at least for another decade is mass numbers, probably much longer than that. We all know that the newer pentiums actually translate x86 instructions into RISC-like instructions, and the core of the processing is done in a much more RISC-like manner.
With the new growing trend toward massive on-die integration (dual cores, memory controllers, etc) I'm wondering if some itanium style-architectures could be used on a chip that translates x86 to EPIC type instructions. With all the space used for mupltiple cores, memory controllers, crypto units, and other goodies that future integration will bring, it doesn't seem to hard to throw in a buttload of extra registers for EPIC-style instructions. Bear in mind that my knowledge of EPIC is very limited, basically "use a buttload of registers and accomplish more tasks in parallel," is all I know.
I'm thinking potentially we could have a bunch of shared registers between multiple cores, this may improve paralellism or do some EPIC-like things. It may lead to a bigger hyperthreading technology, like ultra-threading or something.
I'm just thinking that a lot of the ideas used in EPIC seem potentially compatible with future chip designs, now that we have abandoned the Mhz push and are going to be looking for more powerful chips through integration and features. Anyone have any ideas of the possibilites that are clearer than my lack of expertise? I'm just a dreamer here, I don't wanna hear "that's impossible" replies. This is just high-level dreaming.