Bulldozer-derived successors would largely be targeting ultra low power. Zen-derived architecture would be targeting high performance. Even though the core(&module) sizes would be similar, each architecture would be using different: nodes, macros, cells, etc. Primarily to achieve a niche region for those specific architectures.
BD => Extremely* low cost to produce... thus high profit margin.
ZN => Extremely* high cost to produce... thus low profit margin.
*Reflected to effort needed to produce each processor.
Then, there is thing in the room. Does the Bulldozer successor take what is in Zen and remove SMT and double certain resources cuz Clustered Multitheading? (Same IP means even lower cost to produce)
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8-way L1i -> Dual-threaded Branch Prediction (Really, no change what so ever here... other than more L1i)
Two decodes -> Two micro-op caches
Two integer slices -> Increased width(FP128/128-bit load/store to FP256/256-bit load/store) FPU.
2x L1D/LSQ? etc (Way the architecture is built data communication between slices can be done... *cough*rSMT/CSMT*cough*)
Single interfaces L2 16-way(One huge 1 MB slice) or Dual interfaced L2 2x8-way(Two smaller 512 KB slices that act like one huge 1 MB slice)?
Instruction windows double what is in standard Zen to clustered Zen. (Which means effectively, some should be looking at 2x IPC or 2x EPI over standard Zen) // Only way to increase IPC in modern architecture is to increase the window size.