To me, the current RAM capacity limits seem to be due to the form factors and density of the chips.
Form factors especially.To me, the current RAM capacity limits seem to be due to the form factors and density of the chips.
Does that include the various capacitorless DRAM designs I've seen in research papers for the last several years?No-one has figured out how to build multiple layers of DRAM without requiring exposures per layer, without that it's not worth the cost.
It's not bad. Have you written many other papers like these? If I had to nitpick, I guess I would've liked it being three times more voluminous (as someone who had to write for a class, I know the horrified look on your face after reading that!).Since I haven't seen an explanation of the upcoming process nodes in one place, I ended up writing a paper about it for my Masters a few years ago.
It's not bad. Have you written many other papers like these? If I had to nitpick, I guess I would've liked it being three times more voluminous (as someone who had to write for a class, I know the horrified look on your face after reading that!).
Sustainable High-Performance Instruction Selection for Superscalar Processors
ABSTRACT
Sustainability is a grand societal challenge, which requires our urgent attention given the significant and growing contribution of electronic devices to global warming. The environmental footprint of an electronic device comprises of two major contributors: (1) the embodied footprint due to raw material extraction, manufacturing, assembly, end-of-life-processing, and (2) the operational footprint due to device use during its lifetime. Sustainable hardware design hence requires a holistic approach that encompasses the entire lifetime of an electronic device.
In this paper, we demonstrate how to leverage conventional performance-power-area (PPA) analysis towards sustainable hardware design by investigating the sustainability-performance tradeoff of a non-trivial hardware circuitry, namely the dynamic instruction selection logic in superscalar processors. We assess five previously proposed complexity-effective and power-efficient instruction selection approaches compared to conventional out-of-order (OoO) selection, namely Casino, Load Slice Core (LSC), Forward Slice Core (FSC), Delay-and-Bypass (DnB) and Freeway. We find that Casino, FSC and OoO are Pareto-optimal, optimally balancing the environmental footprint against performance; in contrast, LSC, DnB and Freeway are suboptimal. In addition, based on these insights, we further improve FSC’s environmental footprint and propose FSC++ as a compelling sustainable design point: hardware synthesis to a 7 nm technology node and cycle-accurate FPGA simulation of complete SPEC CPU2017 benchmarks show that FSC++ reduces the environmental footprint by around 40% while degrading performance by only 1.7% compared to an OoO baseline.
Automated CPU Design by Learning from Input-Output Examples
Abstract
Designing a central processing unit (CPU) requires intensive manual work of talented experts to implement the circuit logic from design specifications. Although considerable progress has been made in electronic design automation (EDA) to relieve human efforts, all existing tools require hand-crafted formal program codes (e.g., Verilog, Chisel, or C) as the input. To automate the CPU design without human programming, we are motivated to learn the CPU design from only input-output (IO) examples, which are generated from test cases of design specification. The key challenge is that the learned CPU design should have almost zero tolerance for inaccuracy, which makes well-known approximate algorithms such as neural networks ineffective.
We propose a new AI approach to generate the CPU design in the form of a large-scale Boolean function, from only external IO examples instead of formal program code. This approach employs a novel graph structure called Binary Speculative Diagram (BSD) to approximate the CPU-scale Boolean function accurately. We propose an efficient BSD expansion method based on Boolean Distance, a new metric to quantitatively measure the structural similarity between Boolean functions, gradually increasing the design accuracy up to 100%. Our approach generates an industrial-scale RISC-V CPU design within 5 hours, reducing the design cycle by about 1000× without human involvement. The taped-out chip, Enlightenment-1, the world’s first CPU designed by AI, successfully runs the Linux operating system and performs comparably against the human-design Intel 80486SX CPU.
Our approach even autonomously discovers human knowledge of the von Neumann architecture.
Air based cooling will never be viable for stacked logic/memory of any significantly improved density.No one is forcing them to keep them as sticks. They could theoretically make it a cube of RAM made up of multiple layers of PCB and DRAM chips. Put small spaces in between and use a fan to keep everything running cool. The larger the RAM size, the larger the cube. What would be the drawbacks to that approach?