General purpose CPU's, pipelining sweetspot?

[ynotravid]

Isn't that kinda like calling milk low fat cuz it's 95% fat free.

 

[sao123]

Unfortunately - Jason is right.
100% isnt possible.
95% is about as best it gets. Anything above 95% takes too long to compute, to have the advantage of being right.
What you must remember is: every increment of guaranteed efficiency increases the prediction algorithm in size and running time.

Follow the example:

I have a secret number:
The computer can predict what it is with algorithm (X) in a small time period (T0) and be 95% accurate.
If the guess is incorrect, the computer must guess again. Which takes time T1.
or
The computer can predict what it is with algorithm (Y) in a larger time period (T0 + z), (z is significantly large in size compared to T0 & T1)
and be 98% accurate.
If the guess is incorrect, the computer must guess again. Which takes time T1.

.98(T0 + z) + .2(T0 + z + T1) >= .95(T0) + .5(T0 + T1)
T0 + z + .2(T1) >= T0 + .5(T1)
z > .3T1 (which we have already declared that z is significantly large in size compared to T0 & T1)
There is no performance gain here, actually a loss.

 

[pm]

Unfortunately - Jason is right. 100% isnt possible. 95% is about as best it gets. Anything above 95% takes too long to compute, to have the advantage of being right.
What you must remember is: every increment of guaranteed efficiency increases the prediction algorithm in size and running time.

If you could tell the CPU what branch you plan on taking when (compiler branch hints) then you can achieve much higher values. Alternatively, using architectural methods such as predication you can eliminate the branch altogether.

 

[Sohcan]

95% is about as best it gets. Anything above 95% takes too long to compute, to have the advantage of being right.

I disagree; the tournament predictor in the now 6-year old Alpha 21264 has yet to be matched. While most MPU designs tend to throw more entries into their 2-bit local predictors, there is an asymptotic behavior of misprediction rate vs. predictor size because it cannot account for global branch behavior. The EV6's multilevel tournament predictor adaptively combines local and global branch behavior, and achieves around a 1% mispredict rate in SPECint95 and 0.1% mispredict rate in SPECfp95 (H&P pg. 209). It uses a total of 29K bits, versus, for example, 4K bits (HP PA 8600), 8K bits (P4), and 32K bits (UltraSPARC III) for other MPUs' 2-bit branch prediction buffer schemes. At the same time the more sophisticated branch predict buffer scheme evidently doesn't prevent it from maintaining similar clock speed of its RISC competitors.

And in addition to what pm added, an instruction trace cache can attempt to remove the branch prediction process from the critical path, allowing for more sophisticated branch prediction schemes.

 

[ynotravid]

sao, I'd be with you on this one but what your explaining is how things work now, while what I was suggesting is that there's no telling how things will be done in the future. Even now, look at Transmeta (not there stock ), they have an alternative way of doing things that require different optimizations when compared to traditional x86 CPUs.