They could use a bd arch for my sake as long there is a "performance uplift".
Same Zen core for Summit and Pinnacle. The only differences will be in frequency and possibly out of the box memory support.
They could use a bd arch for my sake as long there is a "performance uplift".
Same Zen core for Summit and Pinnacle. The only differences will be in frequency and possibly out of the box memory support.
Same Zen core for Summit and Pinnacle. The only differences will be in frequency and possibly out of the box memory support.
So we're supposed to believe a slide that says Bristol Ridge has Polaris when it makes claims about Pinnacle Ridge?
Yes its the ppt or beliewe the chief of technology.
Yes that ppt with same arch and performance uplift next to each other. Ppt language.You mean the PPT presented by Mark Papermaster himself?
Yes that ppt with same arch and performance uplift next to each other. Ppt language.
Perhaps he forgot what tock means? Cant blame him if he looks out the window.
I dont think we disagree is near impossible to get any meaningfull ipc increase due to limited time learning from zen tapeout.All that matters in the end is performance increase and not whether it's delivered by perf/MHz increases or by clock speed increases. That's what he was talking about.
I dont think we disagree is near impossible to get any meaningfull ipc increase due to limited time learning from zen tapeout.
Its semantic. If eg max uops altered slightly and we have a new and better imc and it all adds up to eg 1-2% ipc increase is it then a tock?
I am pretty sure he thinks its a tock. And tock as arch change miniscule or not.
When he says tock its tock. Its also on a clearly new node not a slight rev so it makes sense to make a few alterations at the same time.
Yeaa it wasnt me who said tock you know.Whatever you say.
It is entirely possible there are small IPC gains to be had from small tweaks that wouldn't warrant calling it a Zen 2.
Same Zen core for Summit and Pinnacle. The only differences will be in frequency and possibly out of the box memory support.
All that matters in the end is performance increase and not whether it's delivered by perf/MHz increases or by clock speed increases. That's what he was talking about.
“We’re not going tick-tock,” he said. “Zen is going to be tock, tock, tock.”
In recent history they never released a new CPU without a uarch improvement, wether on a new node or a half node, FTR PD was released one year after BD...
It is entirely possible there are small IPC gains to be had from small tweaks that wouldn't warrant calling it a Zen 2.
I'm not saying it will happen, I'm currently in the camp of clockspeed increases and IMC, but it could still be.
Yep. Do you think zen+ comes without any uarch changes?Bristol Ridge.
Bristol Ridge.
You can believe the official AMD roadmap that I retrieved from AMD's website above it if you doubt the other one.
The same architecture doesn't mean the same implementation, clearly. I'm real curious to see what AMD comes up with. I expect some minor improvements (and obviously bug fixes) + a frequency bump. I think 10% more performance is the floor for Ryzen on 12LP and for all our sake, hope they coax a bit more than that out. The 8700K seems like it's a bit pricey, but only because of performance gains over Ryzen.
It is tied to IF, but it's not the sole reason I don't think. Considering AMD's history with IMC's, I'm betting they can make it lower latency with a revision.Memory latency is ultimately tied to IF latency. They either need to tweak IF clockspeed, or they need to give the end-user the ability to change it somehow. Because right now, 1/2 DRAM speed is holding back the platform.
Like you said, ryzen needs for gaming is little higher frequencies and less memory latency.
DF at 2000Mhz or higher would give ryzen some boost.
Changing the speed of the data fabric would likely break the architecture. Improving speed and latency supported by the IMC wouldn't.
Changing the speed of the data fabric would likely break the architecture.