- Apr 5, 2002
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I posted this on THGC, Toms Hardware Guide Community, and I was wondering if anyone here knew the answers to my questions.
Background...
"The Hammer micro-architecture incorporates a dual-channel DDR DRAM controller with a 128-bit interface capable of supporting up to eight DDR DIMMs (four per channel) as seen in the Hammer micro-architectural diagram in Figure 2. The controller will be initially designed to support PC1600, PC2100, and PC2700 DDR memory using unbuffered or registered DIMMs. This translates into available bandwidth to the processor of potentially up to 5.3GB/s with PC2700 memory." - AMD Eighth-Generation Processor Architecture Page 4.
On page 5 it goes on to state...
"The integrated Hammer memory controller has an even more dramatic effect when powering multiprocessing systems. The controller results in an outstanding advance in x86 system architecture scalability by enabling ?glueless? multiprocessing where the available memory bandwidth to the system scales with the number of processors. In Figure 3, an example of a four-processor multiprocessing system is shown. In this configuration, the system is able to support up to 32 DIMMs capable of delivering an extraordinary 21.3GB/s of available memory bandwidth to the system with PC2700 memory."
The reason is that on a 4-way system each processor die can access any DIMM. So 2 channels x 4 sets of channels x 500/3 (~166.667MHz) = 21.333Gb/s.
The only thing I am not sure on is how limiting the Hypertransport for a multiprocessor system will act. I.E say a 4 way system. Hypertransport is a bi-directional, 16-bit, 1600MT/s (Mega-transfers per second), 3.2GB/s data-pathway. See page 7 for a block diagram.
On page 5 of the AMD HyperTransport? Technology I/O Link - A High-Bandwidth I/O Architecture, it shows that the Hypertransport bus is 32-bits wide with a maximum of a 1.6GHz or 1600MHz signal. (1600MHz x 4 Bytes = 6.400GB/s. Now that is one direction. Bi-directional would be 12.8GB/s.
My questions are these...
1. Which is it in the core? 16-bit or 32-bit?
2. Does one use only one direction or both to figure the bandwidth for Hammer using HT?
[rant on]
Also, in the "AMD?s Next Generation Microprocessor Architecture" which was presented by Fred Weber back in October of 2001, one point was "Bandwidth and capacity grows with number of CPUs." This cannot be... But that is another story. [rant off]
I don't know what to exactly believe.
For a single chip setup, the peak bandwidth will be 5.3GB/s. For a multiprocessor system, say a 4-way system, it is peaked out at whatever HyperTransport will allow or what the memory will allow, whichever is smaller or some combination of the two together. That would be... 6.4GB/s (in one direction) x 2 HT data paths = 12.8GB/s for the Hypertransport. The memory would be memory bandwidth of 5.3GB/s per CPU die. (4 CPUs x 5.3GB/s = 21.2GB/s) That is the number that AMD shows but I am not sure it can reach that memory number.
I think it will be something like this.
5.3GB/s for each CPU plus what it can access from the other CPUs' DIMMs. So I think it would be 5.3GB/s (CPU direct)+ 12.8GB/s (Hypertransport) = 18.1GB/s.
Now again this is only my assumption based on what I have read and understand. So if someone out there has a better understanding or has a spin I am not seeing yet, please point it out.
Background...
"The Hammer micro-architecture incorporates a dual-channel DDR DRAM controller with a 128-bit interface capable of supporting up to eight DDR DIMMs (four per channel) as seen in the Hammer micro-architectural diagram in Figure 2. The controller will be initially designed to support PC1600, PC2100, and PC2700 DDR memory using unbuffered or registered DIMMs. This translates into available bandwidth to the processor of potentially up to 5.3GB/s with PC2700 memory." - AMD Eighth-Generation Processor Architecture Page 4.
On page 5 it goes on to state...
"The integrated Hammer memory controller has an even more dramatic effect when powering multiprocessing systems. The controller results in an outstanding advance in x86 system architecture scalability by enabling ?glueless? multiprocessing where the available memory bandwidth to the system scales with the number of processors. In Figure 3, an example of a four-processor multiprocessing system is shown. In this configuration, the system is able to support up to 32 DIMMs capable of delivering an extraordinary 21.3GB/s of available memory bandwidth to the system with PC2700 memory."
The reason is that on a 4-way system each processor die can access any DIMM. So 2 channels x 4 sets of channels x 500/3 (~166.667MHz) = 21.333Gb/s.
The only thing I am not sure on is how limiting the Hypertransport for a multiprocessor system will act. I.E say a 4 way system. Hypertransport is a bi-directional, 16-bit, 1600MT/s (Mega-transfers per second), 3.2GB/s data-pathway. See page 7 for a block diagram.
On page 5 of the AMD HyperTransport? Technology I/O Link - A High-Bandwidth I/O Architecture, it shows that the Hypertransport bus is 32-bits wide with a maximum of a 1.6GHz or 1600MHz signal. (1600MHz x 4 Bytes = 6.400GB/s. Now that is one direction. Bi-directional would be 12.8GB/s.
My questions are these...
1. Which is it in the core? 16-bit or 32-bit?
2. Does one use only one direction or both to figure the bandwidth for Hammer using HT?
[rant on]
Also, in the "AMD?s Next Generation Microprocessor Architecture" which was presented by Fred Weber back in October of 2001, one point was "Bandwidth and capacity grows with number of CPUs." This cannot be... But that is another story. [rant off]
I don't know what to exactly believe.
For a single chip setup, the peak bandwidth will be 5.3GB/s. For a multiprocessor system, say a 4-way system, it is peaked out at whatever HyperTransport will allow or what the memory will allow, whichever is smaller or some combination of the two together. That would be... 6.4GB/s (in one direction) x 2 HT data paths = 12.8GB/s for the Hypertransport. The memory would be memory bandwidth of 5.3GB/s per CPU die. (4 CPUs x 5.3GB/s = 21.2GB/s) That is the number that AMD shows but I am not sure it can reach that memory number.
I think it will be something like this.
5.3GB/s for each CPU plus what it can access from the other CPUs' DIMMs. So I think it would be 5.3GB/s (CPU direct)+ 12.8GB/s (Hypertransport) = 18.1GB/s.
Now again this is only my assumption based on what I have read and understand. So if someone out there has a better understanding or has a spin I am not seeing yet, please point it out.