Haswell overclocking

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jpiniero

Lifer
Oct 1, 2010
16,005
6,479
136
You think they have a huge amount of frequency headroom? Right now the fastest parts turbo up to 4GHz. With mainstream parts and cooling I think they might be able to set base clocks at 4GHz and turbo up to perhaps 4.6GHz or so. That's about 15%. And with mobile they are TDP constrained already.

Considering most Ivy Bridge parts aren't hitting 4.6 at all, I think that's rather unlikely they could get a large enough yield to sell. Maybe another golden sample $2k Xeon.
 

NTMBK

Lifer
Nov 14, 2011
10,398
5,629
136
TSX and AVX/AVX2 are what I believe nudges to the programmers that it's time to really start focusing on multi-threaded performance.

TSX sure, but AVX isn't about multithreading, its about widening vectors within a single thread- which is, frankly, a lot more tricky to squeeze performance out of. Ganging together more and more operations to perform simultaneously is a LOT harder to do than to just have multiple independent threads in flight. I kind of wish Intel would do something like what AMD has done- let their vector units do either a single 256 bit op per cycle, or do two 128 bit ops per cycle. It gets even more mental when you go to the Xeon Phi- 512 bit vectors!
 

Mars999

Senior member
Jan 12, 2007
304
0
0
I have a feeling my 4770k is going to last me a very very very long time. Given Intels performance id expect it be no more than 15% slower than a CPU in 5 years time.

May as well get the K given how long ill be keeping it.

Ditto! I may look at building my next rig after 4770k with a HW-E X99 setup with Nvidia Volta or whatever AMD has out for GPU's then... but that is around 2016-2017 timeframe so at least 3 to 4 years I will be rocking a 4770k I hope as that would be the longest I HAVE EVER OWNED A COMPUTER!!!

Here's to wishful thinking!!!!
 

WhoBeDaPlaya

Diamond Member
Sep 15, 2000
7,414
402
126
5Ghz OC would be awesome for this chip!
That's my target. If you think about it though, that's only a ~55% increase in OCed performance (compared to a i7 920) over the past 4+ years.

Man, we've sure slowed down
 

Hulk

Diamond Member
Oct 9, 1999
5,062
3,546
136
TSX sure, but AVX isn't about multithreading, its about widening vectors within a single thread- which is, frankly, a lot more tricky to squeeze performance out of. Ganging together more and more operations to perform simultaneously is a LOT harder to do than to just have multiple independent threads in flight. I kind of wish Intel would do something like what AMD has done- let their vector units do either a single 256 bit op per cycle, or do two 128 bit ops per cycle. It gets even more mental when you go to the Xeon Phi- 512 bit vectors!


You are correct. I should have been more specific. My point is that Intel is looking to software developers more and more to increase IPC. It is not solely a hardware issue at this advanced state of x86 development.
 

BallaTheFeared

Diamond Member
Nov 15, 2010
8,115
0
71
I'm hoping for ungodly awesome power consumption with a decent overclock and a large undervolt...

lol what's wrong with me?
 

NTMBK

Lifer
Nov 14, 2011
10,398
5,629
136
I'm hoping for ungodly awesome power consumption with a decent overclock and a large undervolt...

Hey, if you want awesome power consumption, then you can go buy an FX-8350 right now!

Oh wait, you meant awesomely small :awe:
 

lagokc

Senior member
Mar 27, 2013
808
1
41
Considering most Ivy Bridge parts aren't hitting 4.6 at all, I think that's rather unlikely they could get a large enough yield to sell. Maybe another golden sample $2k Xeon.

It looks like with Haswell they're going back to fluxless solder which solves a lot of Ivy Bridge's problems at high clock speed. What percentage of Sandy Bridge parts were capable of a 4+ghz base clock? Pretty much all of them?
 

Fx1

Golden Member
Aug 22, 2012
1,215
5
81
Im forced to upgrade due to a poor i7 950 which wont be stable at any overclock it seems. Far Cry 3 crashed 3 times yesterday on stock settings.

I have a motherboard bug which means i get no wifi signal on startup which goes after a reboot. Sometimes my mouse wont move until i unplug and replug it back in.

This PC is a disaster. Its got to go.
 
Mar 10, 2006
11,715
2,012
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Im forced to upgrade due to a poor i7 950 which wont be stable at any overclock it seems. Far Cry 3 crashed 3 times yesterday on stock settings.

I have a motherboard bug which means i get no wifi signal on startup which goes after a reboot. Sometimes my mouse wont move until i unplug and replug it back in.

This PC is a disaster. Its got to go.

Had a PC like that once. My Q6600 based machine definitely was coughing up blood before the end.

You will be much happier with the new PC
 

Fx1

Golden Member
Aug 22, 2012
1,215
5
81
Had a PC like that once. My Q6600 based machine definitely was coughing up blood before the end.

You will be much happier with the new PC

It doesnt really help that im using a wifi module from an old Asus mobo with drivers that are downloaded based on the manufacturers model number.

No idea why the mouse plays up though.

My SSD's are full now since i have 2x120GB Vertex 2's.

My PSU is a 620w so i really need to update that too.

Oh and my DVD drive 4/5 times doesnt recognise that a DVD is present. Then randomly it does.

My Monitor still uses a VGA adapter and even though its 1900x1200 its a really cheap TN panel and i have started to be bugged by the colour issues it has.

I think its all going on ebay and ill just use the money towards the big upgrade in June/July.
 

Pilum

Member
Aug 27, 2012
182
3
81
TSX sure, but AVX isn't about multithreading, its about widening vectors within a single thread- which is, frankly, a lot more tricky to squeeze performance out of. Ganging together more and more operations to perform simultaneously is a LOT harder to do than to just have multiple independent threads in flight.
That's true, nevertheless people manage. They switched to SSE2 from MMX/iSSE, GPGPU has been sucessfully applied to many problem domains, and from initial reports Xeon Phi was well-received by at least some HPC programmers.

Of course you often loose efficiency when porting to a wider SIMD architecture, but that can't be helped. But with efficient data transformation instructions (powerful permute, gather) you can reduce the inefficiencies. That's different from the early days of SSE2 when shuffle instructions were extremely slow due to the lack of a full-width crossbar. And gather should actually allow for vectorization of some algorithms which were not practically vectorizable before.

I kind of wish Intel would do something like what AMD has done- let their vector units do either a single 256 bit op per cycle, or do two 128 bit ops per cycle. It gets even more mental when you go to the Xeon Phi- 512 bit vectors!
This approach doesn't help if you want to increase performance. Let's look at a hypothetical Haswell which aims for the same vector throughput as the actual Haswell, but has 128-bit execution pipes.

You need the following pipes: 4xFMA, 2xVecMisc, 4xLoad, 2xStoreData, 2xStoreAddress = 14 pipes in total. The design needs to be 8-wide to feed the pipes. But of course you not only need an 8-wide x86 decoder and the 14-port backend, but you also need to increase the instruction cache, fetch bandwidth, instruction decode queue, reorder buffer, reservation station, data cache ports, PRF ports and the result forwarding network. With such a wide design you'll probably have to move to clustered execution and add a 2nd PRF. And implement 4-way SMT in order to justify the other expenses. You'll need a deeper pipeline. These changes will increase instruction latencies, probably at least by 2 cycles. Transistor count per core will go up by 25-40%, and you'll loose maybe 30% clockspeed at the same TDP due to the complexity of the chip. Oh, and development/validation costs will double to triple. Also, this chip won't hit the market until 2015, again due to the complexity.

And when you now run your 128-bit code on this chip, you'll find that most programs run as fast as before or even slower because you're now running into ILP issues in addition to the higher latencies and lower clocks. All this on a CPU which is twice as expensive.

Of course you could do a design which is "only" 6-wide and has something like 10-12 execution ports, but such a design would be unbalanced in the ratio of execution and L/S ports, you'd run into bottlenecks and could never fully use your execution resources, but you'd still have to pay a high price for the additional complexity.

So if you consider all the related problems, Intels current designs are probably pretty close to giving optimal vector performance for a mainstream OoO x86 design given the current transistor budget and process limitations. We'll just have to deal with the design-time DLP problems, because there simply is no other practical solution.
 
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