Question HBM Genoa

[Thibsie]

Surprised nobody talked yet about the HBM Genoa Charlie mentioned in a recent article.

Any thoughts?

 

[A///]

Charlie brown?

there's a genoa/epyc thread.

 

[itsmydamnation]

Is that just mi300 with only CPU dies or another product/package?

 

[moinmoin]

Charlie is just rambling about MI300A mostly:

AMD outs Genoa HBM… Sort of… as a GPU

At AMD’s Datacenter and AI day a few weeks ago, the company stealth announced an HBM Genoa CPU, sort of.

semiaccurate.com

The CPU only MI300C doesn't feature at all so Charlie probably missed it.

 

[Joe NYC]

Charlie is just rambling about MI300A mostly:

AMD outs Genoa HBM… Sort of… as a GPU

At AMD’s Datacenter and AI day a few weeks ago, the company stealth announced an HBM Genoa CPU, sort of.

semiaccurate.com

The CPU only MI300C doesn't feature at all so Charlie probably missed it.

The Mi300c was not featured in the presentation, but it does not mean it is not coming out at some point.

Probably left out just so that it didn't steal the spotlight from Bergamo and Genoa-X, which are shipping now.

 

[adroc_thurston]

The Mi300c was not featured in the presentation, but it does not mean it is not coming out at some point.

Too boutique to be an actual product.
MI400 gen maybe, Zen5 is a lot better for silly FMA crunch.

 

[itsmydamnation]

Too boutique to be an actual product.
MI400 gen maybe, Zen5 is a lot better for silly FMA crunch.

more pipes or just more width? ( i hope more 256bit pipes myself)
and i assume more L/S bandwidth.

 

[adroc_thurston]

just more width

Think it's that but I haven't seen the FP results just yet.

and i assume more L/S bandwidth.

Obviously, the thing is kinda monstrous.

 

[Joe NYC]

Too boutique to be an actual product.
MI400 gen maybe, Zen5 is a lot better for silly FMA crunch.

BTW, in the locked thread, you mentioned ~2,400 mm2 ballpark of silicon on the Mi300a, which is what I have been calculating as well.

Which is probably a little more N5 die area than H100 (1000 mm2 vs 800 mm2?) + 1400mm2 of N6. Maybe 200 mm2 for CCDs and 800 mm2 for GCDs.

In theory, if the N6 was mostly SRAM, it could be 1 GB to 2 GB of SRAM.

I wonder if AMD is getting the sufficient bang for the buck on all this silicon...

 

[adroc_thurston]

BTW, in the locked thread, you mentioned ~2,400 mm2 ballpark of silicon on the Mi300a, which is what I have been calculating as well.

That was for X but A is somewhere in the ballpark too.

Which is probably a little more N5 die area than H100 (1000 mm2 vs 800 mm2?) + 1400mm2 of N6

Dylan has accurate die sizes listed in his article.

I wonder if AMD is getting the sufficient bang for the buck on all this silicon...

Well I mean it's an extremely high-margin segment and the solution seems very-very competitive so they're totes okay with piling up on costs.