Help with FPGA

[Stiganator]

I am looking on dinking around and making a little device.

It needs to be able to interface with DDR DIMMs and with SATAII and PATA.

I have been looking at Xilink's Virtex 5 FPGA.

I want to be able to copy the ram to a harddrive automatically, will I need a seperate microprocessor to do this?

Any help or clarifications are appreciated.

 

[Lord Banshee]

Not that i know your answer but i think it will help others.

1) If you are not using a MicroP, what is in the DDR RAM? And how did it get there?

2) You do know that you will have to make a DDR and SATA/PATA Controller with the FPGA or use more IC chips with this.

 

[Stiganator]

let me elaborate more. I would like to develop something like the iRAM 2. But with some more functions. Right now I'm planning on using two DIMMs of 128 MB DDR PC2100 (I have some laying around) and then having a backup program that has manual and automatic features that backs up to a HD or possibly a RAID of 2 Compact flash cards. The Flash is beginning to look more plausible since it draws less power. This is just a proof of concept at this point. I'm a biomedical engineer, so I don't know all that much about IC and PCB design, but I figured it would be a fun and challenging project.

Cliffs:
Want to build a copy of iRAM 2
Using DDR PC2100 and CompactFlash
Don't really know anything
Ummm, yeah.....help?

 

[nd]

You wouldn't need a separate microprocessor for this. I've used the Virtex 4 to interface with DDR2 chips, though we purchased a IP core from Xilinx to do the low-level DDR2 stuff and wrote our own controller to interface it. You could also put a PATA/SATA controller on the FPGA as well.

Note that this would be a rather challenging HDL project for a beginner.

 

[Stiganator]

nd, how long did it take to write your own stuff for the interfacing? More or less I want a way to dump bit for bit what is in the ram drive and then initialize the "container" as it were. Seems relatively simple in principle.

 

[nd]

Originally posted by: Stiganator
nd, how long did it take to write your own stuff for the interfacing? More or less I want a way to dump bit for bit what is in the ram drive and then initialize the "container" as it were. Seems relatively simple in principle.

I didn't do much work on that part, but I believe it didn't take more than a few 8-hour work days to get a working controller interface using the Xilinx IP core. For our case, the controller interface was translating internal bus cycles (in a custom internal bus format that we use to connect components in the FPGA) to driving the DDR2 core signals.

Would you be dumping the DRAM contents to an on-board flash chip directly (i.e., utilizing the raw flash device interface)? Or something else? It wouldn't be too hard conceptually to write the state machine to do the DDR burst reads and flash write cycles, but the devil is always in the details (e.g. buffering data between clock domains).

 

[Stiganator]

Well essentially I would like the functionality to save more that one "state" to the flash memory. That way you can say load a linux distro or a Windows distro with no reinstall work, just a "reload". I would also like the ability to add more Flash memory on the fly or at least with a single reboot and have it automatically added to the free space of the nonvolatile storage. I'm not sure it if requires a file system or not at this point, you'd think a bit for bit copy would do the trick. The project seems simple, and like you said the devil is in the details.

 

[Lord Banshee]

So you are trying to the following?

To use DDR during power, but with no power what ever was saved in DDR is going to be store in flash for power off.

Or are you trying to store DDR memory to Flash Real-Time, If so it ill eventually expire... Flash dies after so many writes. (my Professor had it happen to his autonomous sub)

 

[Stiganator]

only using flash when directed by the user via a driver of when a battery system runs low and it auto backs up before soft powerdown

 

[Lord Banshee]

ok cool.

So you know VHDL? Verilog? Digital Logic

 

[Stiganator]

yeah can't say I do, unless you mean standard and, or , nor stuff. I got a lot to learn on this project

 

[Lord Banshee]

lol, it should be fun

 

[Stiganator]

Anyone want to give me the quick and dirty on the aforementioned?

 

[Stiganator]

Is there anyway that you know of to utilize the PCIe bus for bandwidth for a storage device as opposed to SATA or SATAII. Is there a reason they have a bandwidth of 200MBps on SATAII, is that physical hardware limit or a controller limit.

 

[Megamixman]

You might want to look into the vast array of MPUs that have both an IDE controller and a DDR memory controller. Most companies also have general designs that can be made or even bought. The problem with using an FPGA is that it requires good VHDL knowledge, especially when you are trying to link 2 buses without a controller in the center.

PCIe is a general bus, and thus the bandwidth was made to be able to handle much more bandwidth intensive hardware such as a capture card or a gfx card. The bw of the SATA II HD is a theoretical 300Mbps, but I donut know a single HD right now that can even come close to that theoretical max. They just are not capable of that kind of Bandwidth.

 

[Stiganator]

Well a RAM drive easily exceeds that bandwidth. My goal is to make something that isn't limited to these slow buses, I have an open x16 PCIe slot so I might as well use its 8GB of bandwidth. DDR2100 should theoretically max out at around 2.1GBps right? So, the PCIe bus is really the only bus that can handle the bandwidth. I suppose if I wanted to be a little more hardcore I could try it with faster RAM, maybe some PC5300 so-dimms, that would allow maximum memory storage density on the board.

 

[Stiganator]

Who knows maybe my tinkering will lead to companies actually releasing a better product instead of gouging us on current products that they intentionally make poorly just to recoup costs.

 

[icarus4586]

Sounds pretty nifty, but definitely a pretty big project. You'll definitely want some kind of textbook on VHDL or Verilog. I know that Xilinx FPGAs have the capability to interface with a whole bunch of different bus types, but you may need to get a soft processor core like MicroBlaze from them. Another thing to consider is the price. Depending on how big you want it, an FPGA development board can be fairly expensive. At work we just ordered a dev board with a 400K logic gates Spartan-3, and it was a couple hundred dollars. A Virtex-5 is going to be a lot more than that, but from the sound of it, there's no reason you'd need a Virtex-5.

 

[f95toli]

Also, designing a PCB can than can handle those speeds will be very,very,very difficult. You definitly need a multi-layer board with several ground- and power layers (=very expensive).
This will be a VERY expensive project.

 

[Stiganator]

yeah, I think it might take a while. But here is my first bit of design work. Let me know what you think.

all of it fits in a cdrom sized enclosure.

 

[MrDudeMan]

Originally posted by: f95toli
Also, designing a PCB can than can handle those speeds will be very,very,very difficult. You definitly need a multi-layer board with several ground- and power layers (=very expensive).
This will be a VERY expensive project.

agreed. i dont think you realize just how expensive its going to be. i design and order PCBs on a weekly/biweekly basis and it isnt cheap no matter how you look at it. you are looking at a service charge of 75 dollars and then its around 20 cents per square inch for a 2 layer board, and that doubles for every next even number of layers, so its 40 cents per square inch for 3 or 4 layers, 80 for 5 or 6, etc. you are going to need at LEAST 8, so you are looking at 1.60 per square inch. a cd is 120mm in diameter, so lets just say its a square with 120mm sides, that gives you 14400mm^2, which is roughly 22in^2. at 1.60 per square inch, you are looking at 35 dollars per board.

35 dollars per board gets you a barebone PCB. no solder mask (the green stuff that makes it 100000x easier to solder tiny parts on (i should know, i do this on a daily basis including 128-200pin microcontrollers)) or silk screen (the writing and component ghost on the solder mask). that 35 dollars gets you a bare piece of copper with conductive traces and planes sticking around everywhere, and you cant have that...so you have to get at least the solder mask and if you plan on soldering the components on yourself, you have to get the silk screen as well since it makes it much easier (and by much easier, i mean much much easier). that doubles the price of each board, so you are up to 140ish dollars for 1 board, 200ish for 2, and keep adding 60-70 dollars per board until you get to 50, then you lose the core charge and you get a little bit of a price reduction.

next, you are going to make mistakes big time on the first revision or two. not because you are stupid but thats the nature of the beast. you are going to draw traces wrong, get the wrong parts, get the right parts in the wrong packages, forget to get the vias plated on the interior (this is not the default option sometimes), draw the pads incorrectly or overlap silk screen text, make mistakes regarding the power radiating from bigger components introducing noise into the circuit, and the list goes on and on. so its going to take you at least 3-4 revisions to get it working the way you want (it may work on the first go, which isnt ultra rare, but you will more than likely not get this since its your first time).

if you are accepting of the info i just told you and think you have the motivation to get it done, then i say more power to you and i will help you as much as humanly possible should you ever need it...i just hope you are prepared for it because its a long road and can be very frustrating. you have a great idea IMO and id love for you to see it through to the final product.

 

[Stiganator]

Well seeing as this is kind of a big deal. I am hoping that maybe my school or some local businesses (i.e. Seagate) might be interested in helping. I figure to get a good proto going it will cost a pretty penny(2-4K), but local companies in my area generally don't have a problem dropping a few grand on our projects especially if they might be able to get a cut in the long run. No doubt this will take some time, a lot it if my guess is correct. Hopefully I can finish it before iRAM 3 comes out

 

[Stiganator]

Hears some questions:

1) if I want to run a ribbon type cable from the 5.25 in unit to a 16x PCIe slot, can I still manage a good 4-5 GBps bandwidth? How does that cable length affect things?

2) how much space to must chips need around them for wire routing?

3) Are all the pins on a SO-DIMM independent or are some coupled? Does the slot require 240 leads or are a number just for power?

4) What do you think of the set up, DRAM --> DRAM to Storage Container Chip---> RAID/ General Controller, seems solid or not? I think chips similar to this exist so it should work ok.

 

[GoHAnSoN]

Getting "ribbon cable" to run Pcie ? i wish you good luck.

 

[f95toli]

Originally posted by: Stiganator
Hears some questions:

1) if I want to run a ribbon type cable from the 5.25 in unit to a 16x PCIe slot, can I still manage a good 4-5 GBps bandwidth? How does that cable length affect things?
ok.

No way, the rule-of -thumb is that you multiply 1/(rise time) by 3 to get the analog bandwidth. I am just guessing but I suspect you would need something like 20 GHz bandwidth in order to transmitt 4-5 GBps even over a parallell bus AND you need to keep the SWR under control.
So no ordinary ribbon cable. Moreover, there is no way you can even use ordinary connectors because of the impedance missmatch.
Something like thiss requires some serious microwave engineering.