How do smaller die sizes allow for better performance?

[Smartazz]

What's the exact reason for this, how does 65nm techonolgy allow for higher clock speeds than 90nm technology?

 

[Navid]

That figure is the smallest geometry size that can be made in a particular technology.

So, in a 65nm technology, the gate length of a transistor can be 65nm. While in the 90nm technology, the gate length cannot be any shorter than 90nm.

Gate length is a very important parameter of a MOSFET transistor affecting many of its electrical characteristics. Those electrical characteristics (one of which being transconductance) affect what you can or cannot do with those transistors.

Transistors are used like switches in logic (digital) circuits. The on resistance of a MOS transister with a shorter gate length is lower. So, they can be turned on and off faster. The faster you can turn them on and off, the faster you can run the circuits built with them.

A smaller geometry technology also lets you make narrower integrated metal tracks (with lower parasitic capacitance). This also helps in the same direction (higher speeds) by reducing the load on the transistors.

Fabricating the same circuit in a technology with a shorter gate length results in a smaller die area. Then, the wire tracks going all over the chip to connect different points will be shorter. This reduces the parasitic capacitance of those wires as well. Again, allowing the shorter-gate-length technology to run faster.

 

[OneOfTheseDays]

Originally posted by: Navid
That figure is the smallest geometry size that can be made in a particular technology.

So, in a 65nm technology, the gate length of a transistor can be 65nm. While in the 90nm technology, the gate length cannot be any shorter than 90nm.

Gate length is a very important parameter of a MOSFET transistor affecting many of its electrical characteristics. Those electrical characteristics (one of which being transconductance) affect what you can or cannot do with those transistors.

Transistors are used like switches in logic (digital) circuits. The on resistance of a MOS transister with a shorter gate length is lower. So, they can be turned on and off faster. The faster you can turn them on and off, the faster you can run the circuits built with them.

A smaller geometry technology also lets you make narrower integrated metal tracks (with lower parasitic capacitance). This also helps in the same direction (higher speeds) by reducing the load on the transistors.

Fabricating the same circuit in a technology with a shorter gate length results in a smaller die area. Then, the wire tracks going all over the chip to connect different points will be shorter. This reduces the parasitic capacitance of those wires as well. Again, allowing the shorter-gate-length technology to run faster.

the main problem is that CPU's aren't getting any smaller really, we are simply packing more and more transistors into the given area. thus, local interconnects maybe shorter but global interconnects suffer even further due to the increased RC time constant. also, there are many negative effects that shrinking a transistor brings about, such as leakage current. We will soon run into a wall in terms of how small we can shrink transistors, so improvements are going to have to come from elsewhere.

 

[Soccerman06]

Originally posted by: Sudheer Anne

Originally posted by: Navid
That figure is the smallest geometry size that can be made in a particular technology.

So, in a 65nm technology, the gate length of a transistor can be 65nm. While in the 90nm technology, the gate length cannot be any shorter than 90nm.

Gate length is a very important parameter of a MOSFET transistor affecting many of its electrical characteristics. Those electrical characteristics (one of which being transconductance) affect what you can or cannot do with those transistors.

Transistors are used like switches in logic (digital) circuits. The on resistance of a MOS transister with a shorter gate length is lower. So, they can be turned on and off faster. The faster you can turn them on and off, the faster you can run the circuits built with them.

A smaller geometry technology also lets you make narrower integrated metal tracks (with lower parasitic capacitance). This also helps in the same direction (higher speeds) by reducing the load on the transistors.

Fabricating the same circuit in a technology with a shorter gate length results in a smaller die area. Then, the wire tracks going all over the chip to connect different points will be shorter. This reduces the parasitic capacitance of those wires as well. Again, allowing the shorter-gate-length technology to run faster.

the main problem is that CPU's aren't getting any smaller really, we are simply packing more and more transistors into the given area. thus, local interconnects maybe shorter but global interconnects suffer even further due to the increased RC time constant. also, there are many negative effects that shrinking a transistor brings about, such as leakage current. We will soon run into a wall in terms of how small we can shrink transistors, so improvements are going to have to come from elsewhere.

Recently Ive been wondering at what point die shrinkage stops being useful and we cant do it anymore. Anyone know of that size or is it till yet to be determined.

 

[CTho9305]

how does 65nm techonolgy allow for higher clock speeds than 90nm technology?

This is kinda long. Feel free to ask questions if something is wrong, too hard to understand, or you want more detail.

From the circuit design perspective, circuit performance (I'm just focusing on transistors for now) is affected by resistance and capacitance. If you don't understand what they are, go to the end of this post, then come back up here. See also my explanation of fuzzy math.

The first thing you'll want to know is what a transistor actually looks like, because I'm going to start talking about some of the dimensions of it. Here is a crude drawing of a transistor and here are some quick&dirty 3d pictures (none are to scale). You'll note on the first picture I drew a couple of arrows indicating the "gate length" and the "gate width".

What exactly are you looking at? Well, you really only need to know a couple things: 1. that the red thing is the "gate", and the voltage you put on the gate controls whether the transistor is on or off, and 2. when the transistor is on, it makes a connection between the two sides so current can flow (the big gray blobs are supposed to indicate metal connectors, which hook the transistor up to wires).

A good transistor is strongly "on" when you want to turn it on. Electrically, this means that it allows a lot of current to flow between the two sides, which means it has low resistance. Now, basic electrical engineering tells us that if you have some blob of material, it's resistance is related to how long it is and how wide it is - specifically, a longer conductor has more resistance, and a wider one has less resistance. (So, if you have a 1 foot long wire, it has half the resistance as a 2 foot long wire. If you had 2 1-foot wires next to each other, they'd have half the resistance of just 1 1-foot wire.)

If we look at the transistor like a resistor, we can see that it's length is the gate length*, and its width is the gate width. The 90nm or 65nm indicates the gate length, and since resistance goes down with length, it's clear that the transistor that's only 65nm long will have lower resistance as long as you keep it the same width.

Of course, we like to pack a lot more transistors onto a chip with every generation, and there's another reason smaller is better I'll get to in a moment, so we don't actually keep transistors the same width when you go from 90nm to 65nm - we make them narrower so that the actual resistance stays about the same (2 2-foot long wires next to each other have the same resistance as 1 1-foot long wire).

What's the other reason smaller is better? Well, the way these transistors work is that they have a capacitor at their gate whose electric field turns the transistor on or off. Don't worry why**. If you charge a capacitor to a certain voltage, it likes to stay at that voltage and if you try changing that voltage, it'll change slowly. How quickly you can change it is determined by the capacitance. The capacitance of a capacitor is set by its area divided by its thickness. Since we want fast circuits, we don't want these capacitors to fight back when we try to switch a signal inside a chip, which means we want small capacitors. You'll note that shrinking the gate length shrinks the area of the capacitor, but if we shrink the width we can reduce the capacitance even more. For yet more complicated reasons, we also make it thinner, which cancels out some of the savings, but I won't go into the reason for that***.

So, let's say we have one transistor whose output controls the gate of another transistor. When we go from 90nm to 65nm (scaling everything by 0.7, 0.7*90=65), all of the following things happen:
1. The gate lengths go down
2. The gate widths go down
3. The thicknesses of the capacitors go down

Assuming that our 90nm design had 90nm wide transistors (just for simplicity), and 0.9nm a thick capacitor (unrealistic, but just to make this easy), going to 65nm changes the length and width to 65nm and the capacitor to 0.65nm thick (you'll note that everything scaled by 0.7).

So, computing the new resistance relative to the old one, L went down by 0.7, and W went down by 0.7. Resistance is related to length divided by width, so R = 0.7L / 0.7W. The 0.7 cancels out and the resistance doesn't change. Computing the capacitance, L went down by .7, W went down by .7, so the area went down by 0.7*0.7=0.5 but the thickness went down by 0.7, so the overall capacitance is C = (.7L*.7W)/.7T, which works out to 70% of the old capacitance of the transistors.

When we drive a capacitor load that's 70% of the old load, with the same resistance as before, the circuit gets faster (delay is going to be about 70% of the old delay). I ignored the change in thickness earlier, but what really happens is it makes the transistors faster (the same 70% factor again) giving a total of 50% speedup. When all of your circuits are faster, you can run the clock faster.

I'm pretty sure I was supposed to end up with 50% speedup, but I'm not sure how 0.7*0.7 gives that - wouldn't 0.5 be 100% speedup? It's late, sorry. I don't think I messed up anything serious

-------
Resistance: resistance fights the flow of current. If you imagine wires as pipes and electrical current as water, you can imagine how it's harder to push water through narrower or longer pipes than shorter or wider pipes. Resistors work the same way.

Capacitance: capacitance "fights" changes in voltage (this terminology isn't very good, but it's the best I can come up with). Using the same water analogy, imagine a pipe with water flowing through it. Let's say you suddenly cut the pressure (by turning off a valve) - the water flows out. Turn the valve back on and water starts flowing. What if we had some buckets connected to the side of the pipe, though? Now, when you turn off the valve, the buckets will take a while to empty before water stops flowing out of the end of the pipe. When you turn the valve back on, you won't get water out of the pipe until the buckets have filled up. You can think of capacitance the same way (unfortunately, the length / width stuff doesn't work at all with this analogy). When we're trying to control a transistor, it won't switch until we've drained the pipe all the way, or filled it up all the way, so more capacitance means that takes longer.

Fuzzy math: the actual numbers here are ugly, and multiplying/dividing them is uglier. For simplicity, I'm going to to round 65/90 to be 0.7, and 0.7*0.7 to 0.5, etc.

*Yes, there is also some distance through the orange stuff, but we'll ignore that.
**I'd be happy to elaborate on why, but this post's length is already probably intimidating enough
***I'd be happy to elaborate on why, but this post's length is already probably intimidating enough

 

[BrownTown]

or in easier to understand terms: it just does, so be happy that shrinking process gets you cheaper and faster processors at the same time. Only problem is that silly little leakage current he forgot to mention which goes up as the gate gets thinner, but clearly thats not important

 

[Smartazz]

Originally posted by: BrownTown
or in easier to understand terms: it just does, so be happy that shrinking process gets you cheaper and faster processors at the same time. Only problem is that silly little leakage current he forgot to mention which goes up as the gate gets thinner, but clearly thats not important

The problem with a lot of people is that they don't care how it works, rather that is just works, I for one want to know how things work.

 

[BrownTown]

if you REALLY want to understand you will have to take some college classes in that regard. CTho9305 summerized it really well.

 

[djhuber82]

Originally posted by: CTho9305
Assuming that our 90nm design had 90nm wide transistors (just for simplicity), and 0.9nm a thick capacitor (unrealistic, but just to make this easy),

Not that far off, actually. Gate oxide thickness is 1.6nm for the 90nm process I'm working in.

 

[CTho9305]

Originally posted by: BrownTown
if you REALLY want to understand you will have to take some college classes in that regard. CTho9305 summerized it really well.

I think if you were patient and motivated, you could learn a LOT just by asking questions here - I know I learned a huge amount from pm and Sohcan, among others.

Originally posted by: djhuber82

Originally posted by: CTho9305
Assuming that our 90nm design had 90nm wide transistors (just for simplicity), and 0.9nm a thick capacitor (unrealistic, but just to make this easy),

Not that far off, actually. Gate oxide thickness is 1.6nm for the 90nm process I'm working in.

I figured a factor of ~two was far enough off to say "unrealistic" .

 

[imported_Seer]

Originally posted by: djhuber82

Originally posted by: CTho9305
Assuming that our 90nm design had 90nm wide transistors (just for simplicity), and 0.9nm a thick capacitor (unrealistic, but just to make this easy),

Not that far off, actually. Gate oxide thickness is 1.6nm for the 90nm process I'm working in.

1.6 nm wow!! What clock speeds are you hitting??

 

[djhuber82]

1.6nm gate oxide THICKNESS, not gate length. I'm doing analog design so the clock rates aren't that high (~300MHz).

 

[krotchy]

Originally posted by: Soccerman06
Recently Ive been wondering at what point die shrinkage stops being useful and we cant do it anymore. Anyone know of that size or is it till yet to be determined.

Well according to my circuits 3 class, you pretty much can never be too small. Because according to the formulas, voltage and power go down and switching speed go up with smaller transistors. Essentially the "perfect" transistor would be an atom that has 2 states which are controlible.

At the same time, in physics 3 we pretty much learned that things on big scale change on the small scale, especially when you start getting into the wave properties of matter. Sadly the correspondence principal only goes one way. Cant just assume something macro will be the same in the micro world. So I have no idea how small is too small with transistors.

 

[f95toli]

Originally posted by: Soccerman06
Recently Ive been wondering at what point die shrinkage stops being useful and we cant do it anymore. Anyone know of that size or is it till yet to be determined.

It will stop being usefull once it becomes too expensive to make. I is important to understand that we have been able to make devices (or at least the lithography) much smaller than 65 nm for a long time (20 years or so), it is just routine direct-write e-beam lithography (followed by e.g shadow evaporation), we can make devices with a typical length of 10-20 nm or so (depending on the materials used). The minimum linewidth for "ordinary" deep-UV photo-lithography is around 300 nm or so (with ordinary I mean put a mask on top of the resist, turn on UV, develop) meaning the industry is already using a whole bag of trick in order to reach 65 nm.

However, you can't use this to mass produce circuits; for that you need optical lithography and AFAIK we have already pretty much reach the limit for what is possible. Unless someone can get e.g X-ray lithography up and running soon (not very likely, it is still too expensive) I don't think it will be possible to go on for much longer.

 

[TuxDave]

Originally posted by: krotchy

Originally posted by: Soccerman06
Recently Ive been wondering at what point die shrinkage stops being useful and we cant do it anymore. Anyone know of that size or is it till yet to be determined.

Well according to my circuits 3 class, you pretty much can never be too small. Because according to the formulas, voltage and power go down and switching speed go up with smaller transistors. Essentially the "perfect" transistor would be an atom that has 2 states which are controlible.

At the same time, in physics 3 we pretty much learned that things on big scale change on the small scale, especially when you start getting into the wave properties of matter. Sadly the correspondence principal only goes one way. Cant just assume something macro will be the same in the micro world. So I have no idea how small is too small with transistors.

"too small" is dependant on how creative engineers can be to deal with the problems. Too small could be when the distance is so small that current that tunnels through through transistor when closed is equal the the current when it's supposed to be on. Or too small could be when the presence of 1 extra doping atom in the channel affects the timing by some insane factor. Using fake numbers here since I can't disclose any real data, imagine building a logic path where each gate I said "Well.. the delay though that could be 1 sec or it could be 10 sec. And each gate could behave independent of the other. It's mostly random".

There's lots of challenges and there probably wll be a point where things become too small because as one speaker put it "Exponentials do not last forever". But so far we've been doing a good job of pushing out that limit.