How hard would it be to quad pump the Socket A bus?

[WetSprocket]

I always wondered why wouldn't AMD support quad pumping the socket A interface. I know that it would take a slight modification of the cpu but wouldn't that be an economical way of increasing the speed of the system, especially with the move to 128 bit memory controllers and with the introduction of DDR-II? One other thing too was the 64 bit interface to L2 cache, how hard would it be to move to 128 bit interface, and would that increase performance? I just don't know enough about die structure to know how this would effect performance?

Thanks

 

[WetSprocket]

Thats a good point, Sprocket. They could effectively double the EV6 bus by going quad. But could the Thunderbird handle the extra bandwidth?

 

[SKILL]

the EV6 bus that it uses is able to use upto a 400MHz Double pumped bus i think, so there is no need to quad pump it at the moment, also they are planning to change the L2 interface in the hammer

 

[alpha88]

I believe it would be difficult to redesign the bus to be quadpumped, far easier to just scale up fsb speed or increase width, anyways the next generation will be AMD hyper transit bus (something like that)