Cogman
Lifer
- Sep 19, 2000
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It's not quite that slow. IIRC even with a TLB miss main memory access is like 150-200 cycles. The only time you should have latencies in the range of thousands of cycles is on a page fault.
Good point, my mind is still stuck in the P4 era where memory latencies were much higher.
https://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf
Looks like it ranges from 60->100ns (page 22). So with my rough estimates that translates to 200->300 cycles for a 3.33ghz processor (pretty much exactly what you are saying).