potatoesannCorrect. You're out of luck
Goi The L2 latency is independent of the L1 latency. If you add them up, you're essentially calculating the total latency for a memory access assuming there's an L1 miss and an L2 hitEXACTLY! Which is why DaddyG is right....and why you are right too
In most processors that people are familiar with (the Itanium has some exceptions, and some Alpha chips have some exceptions too), the L2 doesn't get accessed until a L1 miss...so the latency seen by the processor assuming a L2 hit, is the L1 + L2. That's the problem, do you report the latency as seen by the processor, or as given by the time it takes exclusively for the L2 to send information?.... I've heard of some people that have a great dilema when trying to report the latency. The real solution is to explain it both ways I guess.