How will AMD's Zen single thread performance compare to Steamroller's ?

[cbn]

When casting your vote assume both processors are at maximum overclock on air.

 

[Shehriazad]

How in the name of Zorlorc the great Elven wizard are we supposed to make any guesses?

There is literally no material available at all.

So here's my guess...since Zen will obviously have 16 cores that all clock at 5 GHZ naturally while consuming 45W with an IPC gain of at least 125% and on-die 3D HBM as L4 cache...it will obviously destroy Steamrollers so hard that AMD PCs around the world will fall apart in awe (and protest).

Now that this question is solved...what's for dinner?

P.S. Let's make this kind of thread again in a year when we actually got some info (if Zen is still actually happening + any pre-release leaks)

P.P.S. Zen is not modular...Zen will be entirely new and be released in like what...16nm? Which is half the size of anything available on AM3+...if the gain is not at least 30%...there would be no point in AMD betting their last cents on it.

 

[NTMBK]

Magic 8 ball says, "Ask again later"

 

[Flapdrol1337]

Well, the current per thread performance is barely above phenom II level, in a large part due to higher clockspeeds. I expect a dramatic improvement.

 

[jhu]

Well, the current per thread performance is barely above phenom II level, in a large part due to higher clockspeeds. I expect a dramatic improvement.

Piledriver is about on par with Phenom II at the same clock speed.

 

[jpiniero]

Considering AMD has stopped talking about it, I wouldn't be surprised if it gets cancelled.

 

[cbn]

Piledriver is about on par with Phenom II at the same clock speed.

Yes, going by game testing Tom's did in this article, the IPC of Piledriver appears to be around the same level of Phenom II.

 

[schmuckley]

Magic 8 ball says, "Ask again later"

LOL
much later

 

[cbn]

Regarding speculation on Zen, one thing to consider is whether or not AMD will use High Density Libraries for their new core.

http://www.anandtech.com/show/6201/amd-details-its-3rd-gen-steamroller-architecture/2

Looking Forward: High Density Libraries

This one falls into the reasons-we-bought-ATI column: future AMD CPU architectures will employ higher levels of design automation and new high density cell libraries, both heavily influenced by AMD’s GPU group. Automated place and route is already commonplace in AMD CPU designs, but AMD is going even further with this approach.

The methodology comes from AMD’s work in designing graphics cores, and we’ve already seen some of it used in AMD’s ‘cat cores (e.g. Bobcat). As an example, AMD demonstrated a 30% reduction in area and power consumption when these new automated procedures with high density libraries were applied to a 32nm Bulldozer FPU:

The power savings comes from not having to route clocks and signals as far, while the area savings are a result of the computer automated transistor placement/routing and higher density gate/logic libraries.

The tradeoff is peak frequency. These heavily automated designs won’t be able to clock as high as the older hand drawn designs. AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you won’t hit max frequency regardless, and you’ll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings you’d get from a full process node improvement.

We won’t see these new libraries and automated designs in Steamroller, but rather its successor in 2014: Excavator.

 

[geoxile]

In terms of performance/Mhz I expect at least 20% improvement.

But there is a chance that lower max clock will be lower. I definitely don't expect it to come close to competing with Intel's 2016 big core in performance at high power (>35W). From what we've been told AMD is focusing on dense server, embedded, and thin client for Zen and K12, all of which are low-power fields.

From the sounds of it I think that AMD wants to:
1) Lower the bill of materials for OEMs and make it cheaper to adopt their processors
2) Try to penetrate or kickstart novel markets
3) Have a single platform for their products (like shared socket like Carrizo and Carrizo-L but possibly more extensive, i.e. Skybridge).

A large core to fight Intel seems highly unlikely accomplish 1 and 2.

I think AMD's goals with XV will show us what exactly they're seeking to accomplish in the future. That is, maximize perf/W below 35W.

 

[Haserath]

-10%-20%

Yes, that is a negative!

 

[monstercameron]

-10%-20%



Yes, that is a negative!

Hell yeh the DOUBLE double down
MOAR COARS
MOAR CLOCKS
MOAR CACHE
MOAR CASH

 

[lyssword]

bout three fiddy

 

[Xpage]

i see 5 trolls had voted.

I'd guess 20% IPC gain as they need to catch up badly in IPC. It's about double their normal IPC gain, as should be doable as it is a new arch. I don't expect freq. to be as high, no more 4+ ghz, and likely even no more 3.5ghz+. I'd expect turbos to be around 3.2 max, cores running around 2.2-2.6ghz

Think P4 to Core transition. As for # of cores, no idea, probably 4-8 for consumer or enthusiast, and 8-16 for server.

 

[erunion]

Think P4 to Core transition.

What suggests to you that it will be comparable to Conroe? Hope?

 

[Enigmoid]

i see 5 trolls had voted.

I'd guess 20% IPC gain as they need to catch up badly in IPC. It's about double their normal IPC gain, as should be doable as it is a new arch. I don't expect freq. to be as high, no more 4+ ghz, and likely even no more 3.5ghz+. I'd expect turbos to be around 3.2 max, cores running around 2.2-2.6ghz

Think P4 to Core transition. As for # of cores, no idea, probably 4-8 for consumer or enthusiast, and 8-16 for server.

So you expect 1.2x IPC at (2.6 ghz/3.7 ghz : base clocks for a10-7580k and your expected Zen) = 85% the performance of Steamroller.

 

[Arachnotronic]

What suggests to you that it will be comparable to Conroe? Hope?

Jim Keller, duh.

 

[Blitzvogel]

Yes, going by game testing Tom's did in this article, the IPC of Piledriver appears to be around the same level of Phenom II.

Wow, I didn't expect that much of an improvement versus the Athlon and Phenom IIs. Too bad for AMD that I was dead set on going Intel this time around.

 

[Lepton87]

If they can't at least overtake FX 9590 by 20% in ST performance they may as well abandon the desktop market altogether at the very least the retail market and sell to OEMs for AIOs and laptops/tablets and semi custom designs like consoles APUs.

 

[Ramses]

Maybe they are too busy trying to use the 32mil they were gifted for "extreme scale supercomputing" to bother with us right now.

 

[Gikaseixas]

I would say 20 to 30% improvement

 

[Erenhardt]

Are there any dates? It hard to speculate if we don't even know when it will be (or is scheduled to be) released.

If they push it back to 2020 then I expect 2.0x as fast as SR

 

[hungtran]

From the Byrne interview http://venturebeat.com/2015/01/11/w...the-internet-of-things-chip-market-interview/, it looks like he is trying to focus amd away from big chip designs, so it's probably likely zen will be delayed.

 

[schmuckley]

rather its successor in 2014: Excavator.
Well..looks like that ship has sailed :whiste:

 

[videogames101]

Regarding speculation on Zen, one thing to consider is whether or not AMD will use High Density Libraries for their new core.

If they do, Zen will be very slow.

I've worked with an unnamed company's Synthsis/PnR flow on TSMC 28nm, and I can tell you a few things about cell libraries and the above slide.

1. Each color represents a HDL subdivison. In both pictures there, the grey, teal, and purple logic blocks do not look hand drawn, they look like they were placed through Synthesis/PnR. Therefore I don't think AMD's descriptions of those photos are very accurate.

2. "High Density Libraries" are standard industry practice. Most cell libraries come in many flavors, usually named for the height of the each cell. Taller cells are optimized for performance, while shorter cells trade speed for area and power reduction. This is absolutely nothing new or special. It's a standard tradeoff that has always existed for speed/power/area.

3. I can't tell what the multiple colors on the left hand side represent. If those are logic cells, than those cells were placed with a significant number of placement guides to order them in such straight lines, PnR software doesn't do that on its own. It would take a lot of time, probably less than hand drawn transistors I guess. But you probably wouldn't do that, because the software likely knows better anyway. On the other hand, it's possible those sections were still hand drawn like in the first picture, and the photo descriptions are inaccurate.