How will Intel keep its process tech lead in the future?

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Martimus

Diamond Member
Apr 24, 2007
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Just no. Nothing you've typed suggests any understanding of either general or special relativity. That's some pseudo-scientific-sounding babbling that you think sounds interesting. The immutability of the universal speed limit of the speed of light forms the foundation for what appears to at first glance to be throwing the laws of reality out the window. An understanding of the nature of the speed of light is requisite for even beginning to understand the concepts of einstein's relativity theories (specifically, special relativity, which, ironically, is much easier to grasp than general relativity, despite the physical oddities it suggests).

It's very likely, you could have easily made the assumptions that form newtonian relativity though.

I am sorry that you feel that way. I disagree with your assumptions.

Just as there is nothing in my comment that suggested I understand the Theory of Relativity, there is nothing in your post that suggests you understand it either. Neither of us posted enough information to make that assumption about the other persons understanding, yet you made that assumption anyway. I feel no need to prove that I understand the theory, but my course work and academics should be public knowledge if you feel the need to verify anything. My professor for Special Relativity was Dr. Robert Ross. He should remember me, even though it was 11-12 years ago, so you can ask him if you would like to know what he believes my understanding is.

EDIT: Anyway, I am actually glad that you wrote that, since you made me remember that many people know how relative time and length changes between objects traveling at different rates of speed, but most don't seem to understand why. The why is the simple part, and to be honest the math that maps that difference is also very simple (not compared to Newtonian physics obviously, but it is far from complex). I was trying to state what I considered the base reason; nothing can react without an action. I have since thought of an even more base reason, but to be honest, we are getting into semantics at this point. One object will not react to another object in any way until energy is transferred between the two objects in some way. The fastest way that energy can be transferred was postulated as the speed of light by Einstein. While this may or may not be true (Neutrinos travel faster than light, but are believed to not transfer energy, so if true they wouldn't count when it comes to special relativity) it is really unimportant, as most energy transfers at a rate lower than the speed of light. While just thinking about it from the point of view of one of the objects, it doesn't really matter what the object that is reacting with you is doing, all that matters is how it is reacting with you. That is reality for you, just as the way you are reacting to it is reality for it.

Where you seem to be hung up is where Einstein postulated that 'the speed of light in free space has the same value c in all inertial reference frames' which is where most of the differences occur between Newtonian and Einsteinian relativity. While this holds true in practice most of the time, it is a rather strange direct quote to make. The reason for it is based on the fact that no object can react to any object without energy transferring between the two, yet it is written in a way that explains the consequences of this behavior and not the behavior itself. This is the part that makes me give credence the theory that he stole this idea from someone else, but I am not going to make any wild assumptions based on something so insignificant like that. It is just as likely that the quotes I have in my old textbooks are taken out of context, and are only meant to explain the consequences and not the reasons for the relative changes.

I really have gotten nowhere in this post. I still believe that Einsteins theory of Special Relativity is relatively simple, and would have been postulated by someone at some point since the theory behind it is not that complex and it is a simple progression from the work Newton had done. The base formulas are also very basic, and are easy to derive once you formulate that theory.

EDIT 2: While going through some old documents, I found this write-up I wrote years ago. This would be a better explanation, since it was soon after I had gone through all the research:

First, let me start off by explain what I was trying to do when I stumbled upon the Theory we know as Relativity. I was studying the physics and chemistry of biology at a cellular level, and I started to realize that time didn’t make sense by itself. I seemed that it was only the movement of objects in relation to each other, or relative motion. If nothing moved in relation to anything else, time would stand still. And time is only the measurement of relative movement; and not direct movement.

Next I went about trying to figure out what level of relative movement affected time at our level. This was a very difficult question. It was obvious pretty quickly during my research that relative movement at a molecular level definitely affected our interpretation of time. However, certain relative motion below that level seems to affect it as well, while others did not. The conclusion that I came up with was that our interpretation of time was controlled at the molecular level, and that the relative location, direction, and energy (speed/acceleration) of the molecules were what controlled time at our level. I had wanted to call the theory “the theory of relativity”, but that was taken already, so I called it “the theory of relative time”. I planned on finishing up the work and publishing it at some point. What I found later was that my work mimicked Einsteins with his theory of Relativity. No wonder I wanted to call it the same thing, it was the same thing!

The problem was that he assumed a maximum relative motion, while I assumed that relative motion could not be constrained. However, as I looked into it more, I realized that he was right. Or at least partially right. There is a maximum relative motion when it comes to mass, and that would be pure kinetic energy. Einstein made the assumption that light was pure kinetic energy, and there is a lot of evidence to support this. They exert momentum, yet have no measurable mass; so it only goes to reason that they are pure kinetic energy. If this is true, than no object of mass would ever be able to accelerate as quickly as light. Even if it isn’t true, light is very close to pure kinetic energy, so mass is unlikely to be able to accelerate much faster than light. Changing a constant C to a variable for the value of pure kinetic energy allows the theory to go on as stated for all objects of mass.

This brings us to the next problem. Not all reactions require a movement of mass to occur. Energy such as Gravity and Electromagnetic Fields require no moving mass to affect objects, so it is possible that reactions can occur faster than what the theory of relativity would suggest possible. So reactions are possible at a faster than light speed, but no object of mass can accelerate as a faster rate than light; unless light is not pure kinetic energy (if light has some amount of potential energy – in the form of mass – than it would be technically possible to travel faster, but this has not been found).

Finally, the usefulness of what I found is that time travel, teleportation and replication are possible although we cannot control any of them. In order to travel back in time, we would need to set all molecules in the test area in the exact spot they were at the target time, traveling in the same direction, with the same amount of kinetic energy. This would be impossible to do according to the Uncertainty Principle. So unless Heisenberg was incorrect, we will never be able to travel back in time. Even if he were wrong, the resources to do so would be beyond any feasibility, and we would only be able to do it for a limited area; the rest of the universe would continue on at the current time. (Traveling forward in time is actually relatively easy, you just need to stop the relative motion of the molecules in the test area, and restart them at a later time. While freezing something to absolute zero is impossible, it would be possible to freeze it enough to slow down time in that area compared to everything else. Of course we already move forward in time anyway, so this should not be of any shock that this is the easiest of the aforementioned things to do.) Replication and Teleportation are really the same thing, except teleportation destroys the original object. This would be accomplished similar to the method described of traveling back in time. Again, it would be impossible to control if the Uncertainty Principle are true, but if you are able to manipulate objects on a molecular level, you should be able to move all molecules from one space to another and place them in the same relative location, with the same relative direction, and the same relative kinetic energy and the object should react the same. Any energy within the object (gravity, EM fields) would be regenerated on the new object, but it should be nearly the same; so that is would be nearly indiscernible from the original object.
 
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cbn

Lifer
Mar 27, 2009
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They can't avoid competing in the Smartphone market. Even forgetting margins and just looking at revenue though, its hard to see how it can sustain Intel's earnings.

ASPs of Smartphone SoCs: $20-30

Let's assume $30, Intel sells $35 billion Desktop/Laptop CPUs annually. That would require Intel selling 1.2 billion $30 Smartphone chips/year. Since the entire celluar phone(Smartphones/Featurephones etc) market is estimated to be ~1 billion, that's quite inconceivable, since they need to sell low cost chips too.

So Smartphones are not a replacement strategy, rather an expansion of their current market. They want to grow the next 5 years, not stay the same.

In the topic about margins: Margins can be increased with features that differentiate from competitors, and by having a leadership product. You pay extra for Intel chips in the desktop not so much that its x86, but because they have the top chips in the market.

Great points IntelUser2000...and thank you for posting those numbers.

Yes, the asking price looks pretty low on the Smartphone SOC....which makes the question of how Intel will position the future chips interesting.

#1. Will Intel leverage their process tech lead to always win in outright smartphone cpu performance?

# 2. Or will Intel instead use their process tech lead to increase integration over their competitors? This to allow an easier and cheaper to manufacture smartphone platform (FFRD)....with balanced performance.

With that said, I think the real wild card is how much Intel intends to pursue the sale of services...rather than derive income purely from hardware sales.

If Intel intends to make the sale of services a greater part of their future business maybe they focus more on integration (option #2) in order to increase the distribution of their smartphone platform?
 

khon

Golden Member
Jun 8, 2010
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The 450mm wafers mean less EUV machines?

This means lower sales for the companies developing EUV?

Intel's response to this fundamental problem is to buy ASML? Am I getting the jiste of this correctly? (Someone please enlighten me)

Not quite true actually.

450mm means less wafers as compared to 300mm, which means less machines for things like etching, deposition, implantation etc. where you process an entire wafer at a time.

For lithography tools however you do not process an entire wafer at a time, you only process one part at a time, and whether your total wafer is 200, 300 and 450mm, it takes roughly the same amount of time per area, so you simply end up with fewer wafers per hour.

For EUV that means that when going from 300 to 450 mm (125% gain in wafer area), you also lose ~50% in number of wafers per hour. Overall it's a small gain (~2.25 * 0.5 = 1.125 times the previous speed) , but not that drastic. So you still need more or less the same amount of EUV machines.

The reason Intel is putting money into ASML, is that for 450mm you need to develop not only new EUV tools, but also new ArF, KrF and I-line tools, which is a huge investment overall, and this needs quite a lot of capital.
 
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Idontcare

Elite Member
Oct 10, 1999
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The reason Intel is putting money into ASML, is that for 450mm you need to develop not only new EUV tools, but also new ArF, KrF and I-line tools, which is a huge investment overall, and this needs quite a lot of capital.

This is some of the realities of fab operation that I think non-industry folks have no way of realizing or understanding.

People read "14nm fab" and "EUV" and they think the fab itself will only produce/handle 14nm node wafers (the reality is it will be qualified to support capacity for legacy nodes too, like 22nm, 32nm) and that every litho step the 14nm wafer sees during the entire process is going to be an EUV litho step (the reality is EUV is used just for a few critical steps in the process, then when the pitches are relaxed at higher metal levels and so on the legacy litho tools are used).

Process integration is surprisingly simplistic once you get past the barrier to seeing the big picture, but if you haven't had the opportunity to see the big picture then it is a big black box of immense internal complexity.

Does ASML marketing have any fancy java pages or educational pages that would be of use here for the community to understand why a 450mm wafer processed at the 11nm node would need EUV on one part but also still use an I-line scanner (leading edge litho circa 1995) for the 10th metal level?

You or I, and others, can write a thousand words about it and be deadly accurate, but a picture would be worth those thousand words in a heartbeat. Know of any good pics that explain it all in 24bit color?
 

SHAQ

Senior member
Aug 5, 2002
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in the end. I hope we get cheaper chips.

I doubt Intel will be passing the savings on to the consumers. Little competition from AMD and higher process costs means it will be reinvested and possibly some will go to the stakeholders. It will enable them to undercut AMD but I don't see the need for it.
 

ShintaiDK

Lifer
Apr 22, 2012
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Ye, the "cheaper chips" issue is why only 2-3 companies can do 14nm with profit.

Now Intel chooses for us. And thank god for that. Because else too many would pick with shortterm in mind. Or also known as the famous instant gratification.

But lets play with it for a moment for fun sake. If Intel sold us 100$ 3570K. There might simply not be a path to 10nm and 7nm chips. Meaning the world roughly ends at 14nm.

TSMC already needs to do this at 20nm. Basicly no saving for its customers. Same price per transistor as for 28nm.
 

cbn

Lifer
Mar 27, 2009
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Now Intel chooses for us. And thank god for that. Because else too many would pick with shortterm in mind. Or also known as the famous instant gratification.

But lets play with it for a moment for fun sake. If Intel sold us 100$ 3570K. There might simply not be a path to 10nm and 7nm chips. Meaning the world roughly ends at 14nm.

Yep, It is hard to criticize Intel for wanting to maintain gross profit margin when we know they have the problems/challenges mentioned in this paper to deal with.

said:
V. SUMMARY AND IMPLICATIONS
The 30-year-long trend in microelectronics has been to increase
both speed and density by scaling of device components
(e.g., CMOS switch). However, this trend will end as
we approach the energy barrier due to limits of heat removal
capacity. For nanoelectronics, this result implies that an increase
in device density will require a sacrifice, due to power
consideration, in operational speed, and vice versa. Thus, it
appears that we are entering a regime where tradeoffs are required
between speed and density, quite in contrast to the
traditional simultaneous benefits in speed and density from
conventional scaling.
 

ShintaiDK

Lifer
Apr 22, 2012
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We already saw that a single 14nm factory will cost 10B$. I could easily imagine a 7nm factory in the 20B$ range. And also why Intel will most likely be the only company hitting 7nm.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
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We already saw that a single 14nm factory will cost 10B$. I could easily imagine a 7nm factory in the 20B$ range. And also why Intel will most likely be the only company hitting 7nm.

I'd be willing to bet Samsung gets there too, and TSMC. There is no way the global semiconductor TAM sans Intel's portion would not propel at least one foundry with enough revenue and R&D to get to wherever Intel can go.

It'll just be quite a lagging timeline for Samsung/TSMC to get to it because foundries are all about herding cats whereas Intel is more the charging bull.
 

cbn

Lifer
Mar 27, 2009
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Process integration is surprisingly simplistic once you get past the barrier to seeing the big picture, but if you haven't had the opportunity to see the big picture then it is a big black box of immense internal complexity.

Does ASML marketing have any fancy java pages or educational pages that would be of use here for the community to understand why a 450mm wafer processed at the 11nm node would need EUV on one part but also still use an I-line scanner (leading edge litho circa 1995) for the 10th metal level?

You or I, and others, can write a thousand words about it and be deadly accurate, but a picture would be worth those thousand words in a heartbeat. Know of any good pics that explain it all in 24bit color?

ASML has a customer magazine called "Images" --> http://www.asml.com/asml/show.do?lang=EN&ctx=39697&rid=39700

I looked through the 2010 to 2012 issues trying to find something that would help me understand in pictures why EUV is used in some steps and not others....but came up empty handed.



Then I found the ASML EUV FAQ and came away feeling I gained some good general knowledge --> http://www.asml.com/asml/show.do?ctx=41905&rid=41906

A few random excerpts from the FAQ...

A simple explanation on why the shorter wavelength light is needed:

Since lithography is an optical technology, one of the things that limit the resolution of the equipment is the wavelength of the light that is used. Shortening the wavelength of the light means higher resolution and smaller features. Lithography machines have gone from using ultraviolet light with a wavelength of 365 nanometers to “deep ultraviolet” light of 248 nanometers and 193 nanometers, improving the resolution at every step. EUV is the next step, with light of a wavelength of 13.5 nanometers. (An analogy is painting: we use a smaller brush to paint the finer details)

(See quote below) It's expensive!!

The technological challenges that had to be overcome to make EUV a reality were enormous. ASML has spent as much R&D money on EUV as on the previous two generations (ArF dry and ArF immersion) combined.

According to the quote below EUV has the potential to speed things up.....eliminating a slower (or more expensive) step called "double patterning" on the critical layers.

What are the benefits for chip makers?

The current lithography technology has been pushed further than many would have thought possible even five years ago, but this has come at the cost of increasing complexity and shrinking margins of error. The industry has had to reach deep into a bag of tricks to continue shrinking feature sizes. Double Patterning in particular is costly because it increases the amount of lithography exposures per wafer, and thus either reduces fab output or requires more equipment. With EUV, chip makers will return to the former situation in which they expose a critical layer in just one single step. EUV also has a credible path to a resolution of less than 10 nanometers.

According to the following the light source is still a bottleneck to higher throughput:

What issues are still unsolved?

The fundamental technological hurdles have been overcome, but further progress is needed to bring EUV into high-volume production. ASML’s NXE:3100 EUV machine is a pre-production tool; chip makers will primarily use it to become experts in using the technology and to develop the right chip production processes for their fabs, while ASML and its partners continue to improve the technology for it to be ready for high-volume chip production starting in 2013.

For manufacturers to move on to high-volume manufacturing, EUV tools will have to operate at a higher throughput than the first system will offer. The main issue here is the power of the light source: more power means higher throughput. Mask and resist are additional areas where progress has been made but needs to continue.

More info on how EUV and immersion lithography will co-exist:

How will EUV be introduced into volume chip production?

In the past, chip makers have tended to introduce new technology as they switch one from so-called manufacturing “node” to the next. (“Node” here refers to the production of chips with certain feature sizes, for example 32 nanometers or 22 nanometers, using a particular manufacturing technology.) Chip makers would convert all so-called "critical layers" — the layers on a chip that require the highest resolution and precision — to the new technology.

ASML expects chip makers to introduce EUV in a different, more gradual fashion. [/b]Chip makers are expected to use EUV for the most difficult of the critical layers first. When productivity increases — in other words, when EUV systems can process more wafers per hour or per day, making them more economical — additional layers will be converted to EUV.

This means that EUV and immersion lithography will co-exist in the production of the most advanced chips.[/b]

Another link that describes metal layers---> http://en.wikipedia.org/wiki/Back_end_of_line

As of 2011, many commercial processes support 2 or 3 metal layers; the most layers supported on a commercial process is 11 layers, and 12 layers are expected to be supported soon.[13]

The top-most layers of a chip have the thickest and widest and most widely-separated metal layers, which make the wires on those layers have the least resistance and smallest RC time delay, so they are used for power distribution and clock distribution. The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect. Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing cost. [8]

Not sure where EUV would be used? (Apparently it is not the top most layers). At this time I would think EUV is used on the bottom most layers? Or maybe somewhere else in the chip? (Please help if it all possible )
 

khon

Golden Member
Jun 8, 2010
1,319
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Not sure where EUV would be used? (Apparently it is not the top most layers). At this time I would think EUV is used on the bottom most layers? Or maybe somewhere else in the chip? (Please help if it all possible )

EUV would be used for thing like gate, contact, and metal1, meaning the most critical bottom layers.

The top most layers would be older technology I-line or KrF, and the middle layers would be ArF or ArF immersion.

Basically the line width gets more and more relaxed as you go up through the device, so you use the most cutting edge (and hence expensive) technology at the bottom, and gradually change to older less expensive technology for the upper layers.
 
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OCGuy

Lifer
Jul 12, 2000
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They will keep the process lead by continuing to employ the smartest engineers, and making enough profit on each node to recoup the R&D costs.

$$ + Brains = power. I think we proved that at the end of WWII.
 

piesquared

Golden Member
Oct 16, 2006
1,651
473
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How will Intel keep its process tech lead in the future?

They won't.

They're barely there now, 22nm is a marginal improvement over 32nm with 28nm easily matching or surpassing it. The perception is that it is much better though thanks to marketing and shills trolling the forums. There's big money being plowed into R&D from companies other than intel.
 

ShintaiDK

Lifer
Apr 22, 2012
20,378
145
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They won't.

They're barely there now, 22nm is a marginal improvement over 32nm with 28nm easily matching or surpassing it. The perception is that it is much better though thanks to marketing and shills trolling the forums. There's big money being plowed into R&D from companies other than intel.

Calling others for trolls and shills besides the rest of the nonsense?

What a great contribution to the thread.
 
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ShintaiDK

Lifer
Apr 22, 2012
20,378
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I'd be willing to bet Samsung gets there too, and TSMC. There is no way the global semiconductor TAM sans Intel's portion would not propel at least one foundry with enough revenue and R&D to get to wherever Intel can go.

It'll just be quite a lagging timeline for Samsung/TSMC to get to it because foundries are all about herding cats whereas Intel is more the charging bull.

True, the point was more if they could keep or or ends as a generic non interesting foundry. If you need 5-10 years to recoup the investment before moving to the next node, when others continually moves forward every 2 years. Then you are essentially thrown of at the train station while the train moves on.

Looking at TSMC and the transistor cost at 20nm, it seems that border is already reached there. I wonder if TSMC will add 1-2 years to the node progress to get the money need, while still offering an improved transistor/cost ratio to customers. Or simply push on to kill of competition.
 

Blandge

Member
Jul 10, 2012
172
0
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They won't.

They're barely there now, 22nm is a marginal improvement over 32nm with 28nm easily matching or surpassing it. The perception is that it is much better though thanks to marketing and shills trolling the forums. There's big money being plowed into R&D from companies other than intel.

Marginal? See http://www.tomshardware.com/reviews/ultrabook-benchmark-review,3213.html

Performance/Watt is now the most relevant metric, not just pure desktop performance. The 3770K vs 2700K is not the best comparison of 32nm vs 22nm because Intel's finFETs excel at lower power envelopes than desktop 77+ Watts. In the review above consider that the i5-3427 is able to use HD4000 graphics at 17W. Even in Trinity AMD is forced to scale down the number of shaders by 33% in the 17W A6-4455M. The substantial performance gains to see here are due to 22nm allowing higher frequencies and more complexity at 17W.

It will be interesting to see the performance/watt ratio of 22nm Atom.
 

pelov

Diamond Member
Dec 6, 2011
3,510
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Marginal? See http://www.tomshardware.com/reviews/ultrabook-benchmark-review,3213.html

Performance/Watt is now the most relevant metric, not just pure desktop performance. The 3770K vs 2700K is not the best comparison of 32nm vs 22nm because Intel's finFETs excel at lower power envelopes than desktop 77+ Watts. In the review above consider that the i5-3427 is able to use HD4000 graphics at 17W. Even in Trinity AMD is forced to scale down the number of shaders by 33% in the 17W A6-4455M. The substantial performance gains to see here are due to 22nm allowing higher frequencies and more complexity at 17W.

It will be interesting to see the performance/watt ratio of 22nm Atom.

Just a few things to add to that:

- the HD4000, while the same HD4000 in all Intel's IB chips (that have it rather than the lower end HD2500) are running at lower clocks and will throttle down quite frequently. The TDP limitation is still limiting the processor's performance, particularly at the ULV level where the TDP constraints can be quite suffocating.

here's what I mean





The ULV chips, while they're awesome, won't offer you the performance you're looking for and certainly don't offer the performance of their higher TDP brethren. perf-per-watt has improved but not drastically enough to overcome that -- obviously... we're talking half the TDP Keep in mind that it isn't just the GPU that gets limited but also the CPU even without a double GPU/CPU load. As great as Ultrabooks look and though the concept is sound, I don't think the chips Intel sells are yet ready for prime time considering the hardware limitations just yet. They offer enough performance, sure, but if you're paying for a Turbo at X clocks and it can't sustain that for more than a second or two then what exactly are you paying for? What exactly is turbo, then? I've tried playing games on an HD4000 ULV and the performance was jittery and there's noticeable stuttering going on due to those same TDP constraints. It also doesn't help that every Ultrabook on the planet sounds like a jet engine. Point is, just because you've got lower TDP doesn't mean you've got equivalent performance (or anywhere near equivalent) and the form factor can introduce even more issues -- the slim design in ultrabooks, for example, creates heat issues and the fans are generally much louder than regular laptops.

The shrink to 22nm hasn't helped efficiency or clocks or power consumption but rather density the most. Though it's true that all across the board there have been improvements (HD4000 the biggest improvement), it's the potential for viable chips-per-wafer that is the biggest improvement. Die shrinks, whether FinFET or not, don't guarantee you anything as far as power consumption, heat (total output will decrease but density per-mm^2 increases so this can create even more problems), and perf-per-watt + IPC. These factors are difficult to determine because you're dealing with separate architectures, and despite IB being nearly identical to SB, it's still not a straight shrink so you can't claim these improvements are due to the 22nm-trigate node. A smaller node does guarantee smaller chips, though.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
They won't.

They're barely there now, 22nm is a marginal improvement over 32nm with 28nm easily matching or surpassing it. The perception is that it is much better though thanks to marketing and shills trolling the forums. There's big money being plowed into R&D from companies other than intel.

Sometimes I wonder if you have any clue as to how ridiculous your posts sound.

22nm is marginal to 32nm, but 28nm easily surpasses it?
 

cbn

Lifer
Mar 27, 2009
12,968
221
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It will be interesting to see the performance/watt ratio of 22nm Atom.

Yes!

I also think the radio performance (on the atom SOC) would be particularly interesting.

http://semiaccurate.com/2011/11/22/intel’s-analog-shrink-is-for-real/

If you read the above semi accurate article they talk about Intel releasing a dual core atom (Cloverview?) with integrated Wifi on 32nm......

Where it gets interesting IMO is the discussion I have read regarding analog needing larger xtors.

From the Nov. 28,2011 comment (underneath the linked semi-accurate article) written at 2:42 pm:

A transistor is a transistor. The size depends on packaging restraints and cost. It's not like they're using larger transistors because they have to or anything

Actually they do. The analog properties of a transistor are highly dependent on its size. Using minimal size digital transitors would lead to amplifiers with no gain, no power handling capability, high noise, etc. etc.

A lot of analog IC design is in fact deciding what size of transistor to use and how to lay it out on the die.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
Where it gets interesting IMO is the discussion I have read regarding analog needing larger xtors.

Its true for digital cmos as well, not just analog. That is why the density of sram, for example, varies between L1, L2, and L3. It is also the reason why xtor density for GPU's is so different than that for CPU's. Or low-clockspeed ARM designs versus high-clockspeed designs.
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
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If you read the above semi accurate article they talk about Intel releasing a dual core atom (Cloverview?) with integrated Wifi on 32nm......

That chip with integrated WiFi isn't anything near production. We'll see integrated WiFi in the future, but they estimate it'll happen around ~2015. What will happen earlier is Atom with 3G and 4G integrated.

Keep in mind that it isn't just the GPU that gets limited but also the CPU even without a double GPU/CPU load.
I think that's the whole point of having cTDPup, once manufacturers start using it. What I found interesting is the power usage when running those games. cTDPup at 25W will basically allow iGPU to run at full throttle while allowing the Core i5 3427U to run at base frequency of 2.3GHz.

TDP isn't just about the cores either. You see on the measurements, the power usage excluding CPU core and the iGPU is similar ~4W, likely taken up by the uncore. 4W is insignificant when the whole chip is using 35-40W, but quite a bit at 16-18W. When running in cTDP down 14W mode, the base frequency goes down to 800MHz. cTDPdown is probably what enables Tablet form factor and the assumption is you won't need anything much higher than 800MHz since you'll be on battery doing consumption things. Turbo is just for responsiveness.

The shrink to 22nm hasn't helped efficiency or clocks or power consumption but rather density the most.
I don't think you'll see a day again where you'll see huge power efficiency gains with process alone. Even Ivy Bridge's gains where Intel says its more efficient at intermediate(in other words, not Turbo peak, Base, or LFM) levels is due to the chip having more voltage frequency levels, rather than process.

Basically the feeling we got when Intel announced their 22nm giving magical benefits is a lot of PR talk. It's probably true, but it won't be seen until we see architecture made for 22nm. Being able to gang fins for more drive current, or that it'll allow steeper frequency curves are probably merely more "ingredients" for the process cooks that's reserved for new architecture, maybe.

That was same for Power Gating shown for Nehalem. Sure, it showed lower power for idle desktop configs, but it didn't achieve better battery life over Penryn systems. Nehalem EX did not use Power Gating, the successor Westmere EX did.
 
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OCGuy

Lifer
Jul 12, 2000
27,227
36
91
Calling others for trolls and shills besides the rest of the nonsense?

What a great contribution to the thread.

Just look at his other posts on this forum and others using the same pseudonym . You'll understand.
 
Dec 30, 2004
12,554
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EUV is late to the party because there are still several major issues with the power sources, mask infrastructure and other technologies. Because of the lack of adequate power sources, EUV throughputs are running about 4 wafers an hour right now. The industry requires throughputs of around 100 wafers an hour to make EUV economically viable in production foundries.

Intel inserted its initial 193nm immersion scanners (deep ultraviolet sources based on argon fluoride (ArF) lasers) at its 32nm node. Nikon Precision was the sole supplier of 193nm immersion scanners for the "critical layers" at Intel’s 32nm node.

At 22nm, Intel rolled out its TriGate transistor technology. The company is still using 193nm immersion scanners for the critical layers at that node. The critical layers are reportedly being split between ASML and Nikon.

Then, at 14nm, Intel will continue to use 193nm immersion for the critical layers. And it will implement an undisclosed type of "pitch-halving" (double patterning) technology at that node. Intel’s 14nm process is expected to be ready by 2013. Like 22nm, Intel will probably use both ASML and Nikon for the critical layers.

At 10nm Intel is keeping its options open:

http://semimd.com/blog/2012/02/12/intel-wants-euv-but-firm-keeps-options-open/

Even though EUV is still a technical challenge, 450mm needs only money and vendor support. It is interesting to note that ASML was one of the reluctant vendors to start 450mm. They kept saying that ASML would only do 300mm EUV first. It was expected that tool vendors would ask semiconductor companies to share the cost of 450mm development. Intel, Samsung, and TSMC were already pushing for 450mm in order to maintain a reasonable cost structure for the semiconductor industry:

http://www.eetimes.com/electronics-news/4076946/Intel-Samsung-TSMC-push-for-450-mm

There is summary of the Intel and ASML agreement at the following URL:

http://www.electronicsweekly.com/Articles/10/07/2012/54092/intel-to-pay-4bn-for-15-stake-in-asml-to-accelerate-450mm-and-euv-development.htm

Most of the money will go to 450mm lithography. Intel has mastered "pitch-halving". They will probably use quadruple patterning at 10nm if EUV is not ready. This would, however, increase the costs. They are pushing for 450mm to maintain the cost structure.

if EUV isn't ready at 10nm, why even bother with it, just so they can run it at 7nm and then 5/4nm? also, welcome
 
Dec 30, 2004
12,554
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I doubt Intel will be passing the savings on to the consumers. Little competition from AMD and higher process costs means it will be reinvested and possibly some will go to the stakeholders. It will enable them to undercut AMD but I don't see the need for it.

Hopefully they won't. That should give AMD some breathing room and an incentive to keep trying.

However, it may just make the path paving to smartphones that dock into a desktop station happen all that much faster if people start saying "why am I buying this expensive stuff again?"
 

Ferzerp

Diamond Member
Oct 12, 1999
6,438
107
106
To posit that they would lose their lead would be to have some competitor in mind who can make profits such that they could both close the gap, and out-innovate Intel.

No current organization comes to mind.
 
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