HyperTransport vs PCI Express

[LegacyLover]

I was going through the HyperTransport and PCI Express specs, it looks like both are almost same except differences in signalling. From higher perspective, I feel they both are having same features. Because HyperTransport is by AMD & PCI Express is by Intel, they made the protocol, named differently and trying to market with their own way? Any comments???

 

[RaynorWolfcastle]

Although both are designed for high speed point-to-point signaling schemes they are not the same in intent (or in application for that matter). If I'm not mistaken, PCI-Express was designed to be compatible with the older PCI protocol; not electrically, but at the protocol level.

Intel has a competing point-to-point bus in the works to replace their outdated FSB structure, but it still hasn't made it out the door. As far as I know, their CSI bus is supposed to be similar to Hyper-Transport; although Intel obviously claims that it's much better. Until Intel gets CSI out, it's going to have to keep piling cache on its chips to try to hide the fact that it's multi-CPU solutions are lacking bandwidth to system RAM.

 

[Missing Ghost]

I would like to know why hypertransport is used to interconnect cpus and chipsets while pcie used to interconnect integrated peripherals and expansion cards. The only hypertransport expansion cards I've seen were for Infiniband.....

 

[borealiss]

pci-express is mainly a peripheral protocol. it does not have a lot of system features that are used in hypertransport. PCIE was meant to connect mainly I/O devices. PCIE and HT can both be used as I/O interconnects between many devices that sport a PCIE or HT bridge controller. where HT differs mainly is its support specifically for communicating with microprocessors. HT has specific system management support that aid in ACPI handling, interrupt delivery, etc... If you look at the HT 1.x spec, there are specific message protocols for items like interrupts, stpclk, c-state transitions, and other ACPI features. there's also complex interrupt handling messages that can be delivered via HT that i'm not quite sure exist on PCIE.

PCIE in its current iteration does more things than HT in its current form to support multiple devices sharing the same I/O lines. on-the-fly lane splitting and bidirectional I/O drivers that exist make it very easy to have a PCIE controller adapt to differing I/O conditions if the PCIE controller is designed to do so. HT has dedicated lanes for upstream and downstream traffic and is not bidirectional.

this is not to say a protocol could not piggyback on top of PCIE for all of the system management quirks that HT covers, but it would probably have more overhead, almost like TCP/IP over ethernet vs. ethernet supporting IP addresses natively. there are implemenations (ATI boards) that have the southbridge hanging off of a PCIE controller, so there probably is some type of interrupt messaging protocol that piggybacks on PCIE. i may be wrong, however.

 

[RaynorWolfcastle]

As I stated in my post, the PCIe protocol is that of conventional PCI, only the physical layer is changed. There are interrupts and all the other standard PCI features.

It is interesting to note that while both PCI and PCIe have the same protocol they differ strongly in topology. In effect, the PCI protocol was designed for a bus topology, but is now being used in PCIe for something which is actually a star topology. This in turns means that the PCIe hub has to mediate all this traffic and make it appear to all devices that they are using a bus, which requires significantly more computing.

 

[Peter]

PCIE, like PCI, is a _peripheral_ interconnect. For inter-CPU traffic, you'd need cache coherency traffic on there as well, which is something peripheral busses simply don't do.

HyperTransport on the other hand is intended to be more of a CPU and core chipset interconnect than a peripherals connection.

They both look exactly like PCI to software, btw.

Also, the PCIE topology maps onto the PCI software picture such that every PCIE link appears to be a separate "bus" with its own PCI-to-PCI bridge and a single device on it.

Neither HT nor PCIE allow "devices to share the same I/O lines", it's all point-to-point. On top of that, HT lets a device be a "tunnel" implementation, in that it has an incoming HT link and an outgoing one for daisy-chaining the next chip onto it. PCIE doesn't have that.

PCIE of course does have an interrupt messaging concept; it wouldn't even work for peripherals without one.

 

[imported_Student]

Hi,

could anyone help me to understand main principles of HT:
- how does an ht node know what Unit ID it should start transaction to and how is Unit ID and system addresses are mapped so that a tunnel node knows where to send the packet?
- how is an ht node organized to connect legacy devices to it (for example, a microprocessor or a RAM, or a PCI devices to be connected to the HT bus);
- are CLK and CTL lanes the only bus lines that not packetized ?
- how, for instance PCI device's frame# like control signals, are transfered to destinations
and other questions.

would you help me - a student ?

 

[fighterpilot]

And for a 2000MHz HT Bus, is it correct for CPU-Z to show a 1000MHz speed? I know it is probably something like DDR or dual-channel, where the effective rate is doubled, but why?

 

[Bob Anderson]

Originally posted by: fighterpilot
And for a 2000MHz HT Bus, is it correct for CPU-Z to show a 1000MHz speed? I know it is probably something like DDR or dual-channel, where the effective rate is doubled, but why?

Quote from AMD:


Q: What is HyperTransport? technology?

A: HyperTransport? technology is a high speed, high performance point-to-point link for interconnecting integrated circuits on a motherboard. It can be significantly faster than a PCI bus for an equivalent number of pins. HyperTransport was previously codenamed Lightning Data Transport, or LDT.

HyperTransport technology was invented by AMD and perfected with the help of several partners throughout the industry. It is primarily targeted for the IT and Telecomm industries, but any application where high speed, low latency and scalability are necessary can potentially take advantage of HyperTransport technology.

Endquote

---------------------------------

Yes, CPU-Z will show 1000 Mhz, but the effective rate is 2000 Mhz because two signals can be sent per cycle, one signal at the beginning of the cycle and one at the end.

-Bob

 

[Calin]

The quad-pumped FSB from Intel sends data four times a clock - the idea is that the data transfer paths are fast enough, while the logic/command paths (which are longer) are much slower. So, the FSB's change from reading to writing (from processor to northbridge) is inherently slower. Data transfer, meanwhile, can be much faster - the logic that do data transfer is very simple compared to the rest.
The HyperTransport is somewhat similar - it decouples the inherently slower operations from the inherently faster ones (data pumping is very fast, as long as both sides allow it).

 

[Peter]

Intel's FSB is most prominently held up by the fact that it isn't bi-directional ... unlike HyperTransport and PCIE.

 

[gbuskirk]

- how does an ht node know what Unit ID it should start transaction to and how is Unit ID and system addresses are mapped so that a tunnel node knows where to send the packet?

A HT node encodes its own UnitID in request packets. These are routed by Address. In response packets, it encodes the UnitID that was in the request packet it's responding to. Responses are routed by UnitID & SrcTag fields.

- how is an ht node organized to connect legacy devices to it (for example, a microprocessor or a RAM, or a PCI devices to be connected to the HT bus);

PCI devices would be on a PCI bus off of a HT-PCI bridge device. A peripheral like a RAM or a coprocessor could be on a HT tunnel or cave device. GDA Technologies licenses intellectual property for HT cores at http://www.gdatech.com

- are CLK and CTL lanes the only bus lines that not packetized ?

Take a look at the HT spec at http://www.hypertransport.org. There are other non-"packetized" discrete signals associated with resets, etc.

- how, for instance PCI device's frame# like control signals, are transfered to destinations

No time to write a dissertation. Refer to the spec I linked above. Also, Mindshare publishes a fine book on HT at http://www.mindshare.com.