pci-express is mainly a peripheral protocol. it does not have a lot of system features that are used in hypertransport. PCIE was meant to connect mainly I/O devices. PCIE and HT can both be used as I/O interconnects between many devices that sport a PCIE or HT bridge controller. where HT differs mainly is its support specifically for communicating with microprocessors. HT has specific system management support that aid in ACPI handling, interrupt delivery, etc... If you look at the HT 1.x spec, there are specific message protocols for items like interrupts, stpclk, c-state transitions, and other ACPI features. there's also complex interrupt handling messages that can be delivered via HT that i'm not quite sure exist on PCIE.
PCIE in its current iteration does more things than HT in its current form to support multiple devices sharing the same I/O lines. on-the-fly lane splitting and bidirectional I/O drivers that exist make it very easy to have a PCIE controller adapt to differing I/O conditions if the PCIE controller is designed to do so. HT has dedicated lanes for upstream and downstream traffic and is not bidirectional.
this is not to say a protocol could not piggyback on top of PCIE for all of the system management quirks that HT covers, but it would probably have more overhead, almost like TCP/IP over ethernet vs. ethernet supporting IP addresses natively. there are implemenations (ATI boards) that have the southbridge hanging off of a PCIE controller, so there probably is some type of interrupt messaging protocol that piggybacks on PCIE. i may be wrong, however.