IBM's 22nm PDSOI process for Power8

[SocketF]

It is rather old, but I havent seen it here, yet:

22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL, IBM Semiconductor Research and Development Center

http://www-03.ibm.com/technology/news/iedm_2012.html

In the paper the key design rules are given as follows:
Contacted gate pitch: 100 nm
N-P Active Space: 72
Metal 1-5 Pitch: 80nm
6-7: 144 nm
8-10: 288nm
11-13:640nm
14-15: 2400nm

Source: SA-forum

Do we have similar data of GF's 28nm process? Not sure if they have been posted somewhere.

 

[paigeadele]

so far I have not seen these boards for sale or pictures of any owned by anybody...

http://www.enterprisetech.com/2014/10/08/tyan-ships-first-non-ibm-power8-server/

I've also contacted tyan sales, twice ... no reply. Vaporware?

Still interested, read up a bit on FD-SOI vs PD-SOI, I can see in the past its not uncommon with new + releases (ie: POWER 7 vs POWER 7+) to adopt new processes for their chips. I wonder if there's any advantage for them to switch to FD-SOI ?

Ivy is also 22nm (but neither PD nor FD? they're trigate?) SOI http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf

So asides from SMT what are some other advantages besides the (RISC vs CISC) advantage which I totally agree with but doesn't make any difference in the "real" world?

 

[SarahKerrigan]

so far I have not seen these boards for sale or pictures of any owned by anybody...

http://www.enterprisetech.com/2014/10/08/tyan-ships-first-non-ibm-power8-server/

I've also contacted tyan sales, twice ... no reply. Vaporware?

Still interested, read up a bit on FD-SOI vs PD-SOI, I can see in the past its not uncommon with new + releases (ie: POWER 7 vs POWER 7+) to adopt new processes for their chips. I wonder if there's any advantage for them to switch to FD-SOI ?

Ivy is also 22nm (but neither PD nor FD? they're trigate?) SOI http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf

So asides from SMT what are some other advantages besides the (RISC vs CISC) advantage which I totally agree with but doesn't make any difference in the "real" world?

P8 can decode, issue, and retire eight ops per cycle, sustained, compared to four on current Intel cores. This is especially convenient for multithreaded loads, because it can issue from all eight threads simultaneously, but has advantages for single-threaded loads as well.

It also has a high-capacity and high-performance cache hierarchy, including 8MB per core of eDRAM LLC and large L2 and L1 SRAM caches (512KB and 64+32KB respectively.)

While the above does matter for single-thread performance, P8 shines far more on MT than on ST, primarily due to the extremely wide SMT. We can see this paying off on some of the benchmarks that have been released thus far, especially SAP SD-2.