Originally posted by: jones377
I don't think this has been posted yet. Real World Technologies posted a very detailed article on the Conroe Microarchitecture here.
Superficially Conroe looks alot like Yonah but when we dive deeper there are major changes. Some highlights:
* Direct L1-L1 cache transfers between the cores
* 1 Complex, 3 simple decoders. Up from 1+2
* One 128-bit FADD plus one 128-bit FMUL vector SSE instructions per cycle. Twice that of P4/K8!
* Memory disambiguation. Completely new feature to x86 MPUs AFAIK
* SSE4 CONFIRMED. Would have been included in Tejas too. Nice but not general purpose in nature so don't expect much in most cases.
Even more info in this https://www35.cplan.com/cbi_export/PS_MATS001_278703_125-1_FIN_v1.pdf">presentation</a>
id: idf
username: spring2006
good info, i hadnt heard much beyond that it was a 4 issue core.