Idontcare, a technical explanation please?

[Arachnotronic]

I'd message this to Idontcare privately, but the answer to said question is likely to require significant effort and would not want his wisdom/knowledge to go to waste, so I'm asking it in a thread publicly, and perhaps other semiconductor experts can answer for me as well:

I have seen on the forums/online, a discussion of Intel's 22nm versus TSMC's 20nm. The idea is that on the interconnect/metal stack side of things TSMC has an M1 pitch of 64nm (the best that can be done with double-patterning) at 20nm (and the "16nm" node) while Intel is at 80nm and is utilizing single-patterning.

So, the claim from TSMC is that 16nm will be using the 20nm metal stack, which means that going from 20nm -> 16nm, there will be very little density improvement. But on the other hand, Intel is claiming that from its 22nm node to the 14nm node, it sees the traditional 2x density improvement. But of course the limits of double-patterning keeps the minimum M1 pitch at 64nm for Intel as well.

So my question is this: what's the deal here? What is Intel doing at 22nm that lets it get away with being a "22nm" node, what is it getting away with to allow it to get the full density benefit at 14nm while TSMC doesn't? Is there more to density than just the M1 pitch? Is there more to defining the density at the metal stack level than M1?

My background, unfortunately, is not EE/physics, but I'm a quick learner...so drop all the jargon you need to.

Much gratitude to anybody who replies!

 

[chernobog]

Intel does not share the same standard as other foundries so its hard to answer.

I am curious on how idontcare will respond.

 

[Ben90]

While not the most technical answer available, the names of nodes don't really mean anything. TSMC's 45nm got renamed to 40nm for marketing reasons while Intel's 45nm was still superior in most dimensions. I'm having a hard time finding charts of the past that help illustrate the point.

Remember that the feature size of transistors are only one part of total performance. Switching characteristics matter just as much if not more.

 

[aigomorla]

Intel does not share the same standard as other foundries so its hard to answer.

I am curious on how idontcare will respond.

+1

intel's nodes are kept highly confidential.

TSMC for example didnt use high-k gates in there designs for a very long time after intel has.

 

[NostaSeronx]

intel's nodes are kept highly confidential.

^--22-nm Intel

The TSMC for example didnt use high-k gates in there designs for a very long time after intel has.

The TSMC 28-nm process uses the same HKMG setup as Intel 32-nm.

 

[AtenRa]

I'd message this to Idontcare privately, but the answer to said question is likely to require significant effort and would not want his wisdom/knowledge to go to waste, so I'm asking it in a thread publicly, and perhaps other semiconductor experts can answer for me as well:

I have seen on the forums/online, a discussion of Intel's 22nm versus TSMC's 20nm. The idea is that on the interconnect/metal stack side of things TSMC has an M1 pitch of 64nm (the best that can be done with double-patterning) at 20nm (and the "16nm" node) while Intel is at 80nm and is utilizing single-patterning.

So, the claim from TSMC is that 16nm will be using the 20nm metal stack, which means that going from 20nm -> 16nm, there will be very little density improvement. But on the other hand, Intel is claiming that from its 22nm node to the 14nm node, it sees the traditional 2x density improvement. But of course the limits of double-patterning keeps the minimum M1 pitch at 64nm for Intel as well.

So my question is this: what's the deal here? What is Intel doing at 22nm that lets it get away with being a "22nm" node, what is it getting away with to allow it to get the full density benefit at 14nm while TSMC doesn't? Is there more to density than just the M1 pitch? Is there more to defining the density at the metal stack level than M1?

My background, unfortunately, is not EE/physics, but I'm a quick learner...so drop all the jargon you need to.

Much gratitude to anybody who replies!

Transistor density is a combination of Contacted Gate Pitch (Gate Pitch), Gate length(Lgate) (that one affects the transistors size itself) and Metal Pitch.

Contacted Gate Pitch (Gate Pitch) gives you the minimum distance you can put two transistors together.

Metal Pitch is the size of the metal wires.

So, even if you keep the same Metal Pitch, if your Gate Pitch is smaller then you will get higher density. It would be much higher if you had both but still it will give you higher density than before.

Im sure IDC will explain it better

 

[Arachnotronic]

Transistor density is a combination of Contacted Gate Pitch (Gate Pitch), Gate length(Lgate) (that one affects the transistors size itself) and Metal Pitch.

Contacted Gate Pitch (Gate Pitch) gives you the minimum distance you can put two transistors together.

Metal Pitch is the size of the metal wires.

So, even if you keep the same Metal Pitch, if your Gate Pitch is smaller then you will get higher density. It would be much higher if you had both but still it will give you higher density than before.

Im sure IDC will explain it better

AtenRa,

Thanks for the explanation; definitely helpful!

 

[Exophase]

Will still be eager to see if Intel's 14nm really does scale as well as its predecessors did. Lower scaling improvement could go a long way to explaining why Intel is releasing Broadwell for mobile only (or at least well ahead of desktops if they ever do it); at this point desktop's only worth it if the chip gets cheaper and/or faster CPU, using less power or having a faster GPU aren't worth much to Intel is this space. While mobile has a strong focus on better perf/W and stronger IGP.

 

[Arachnotronic]

Will still be eager to see if Intel's 14nm really does scale as well as its predecessors did. Lower scaling improvement could go a long way to explaining why Intel is releasing Broadwell for mobile only (or at least well ahead of desktops if they ever do it); at this point desktop's only worth it if the chip gets cheaper and/or faster CPU, using less power or having a faster GPU aren't worth much to Intel is this space. While mobile has a strong focus on better perf/W and stronger IGP.

The 14nm node will bring the traditional scaling improvements according to several recent presentations at investor conferences. I think the Broadwell not coming to LGA is done primarily because Intel can keep milking by then higher margin 22nm parts in a non-critical segment while directing the new 14nm capacity to where the volume is - mobile.

 

[Exophase]

But if what AtenRa says is true how can it be? I mean, he said it'd give higher density but not as much scaling as before, so if what you say is true he'd have to be wrong. And I don't see anything that sounds wrong with his explanation.

TSMC has also promised a lot with 20nm but I'm hearing all sorts of rumors that it'll be nowhere close, so I'm really going to wait and see what everyone brings all around and not rely on official statements, even ones made to investors :/

 

[AtenRa]

The 14nm node will bring the traditional scaling improvements according to several recent presentations at investor conferences. I think the Broadwell not coming to LGA is done primarily because Intel can keep milking by then higher margin 22nm parts in a non-critical segment while directing the new 14nm capacity to where the volume is - mobile.

Look at NostaSeronx picture, At the same 22nm we have more than one process. The High Performance is the one used in Server/Desktop parts. It has the highest density and the highest electrical characteristics. On the other side, the LP process is bulkier(less density) but with way lower currents (Idsat/Ioff). You give up performance (frequency) for lower consumption (current).

If im not mistaken (IDC will confirm or not this one), the LP process its easier to make than the High Performance. The smaller (Gate Pitch) and higher current HP process is more difficult to design/manufacture than the rest. Its why the LP process is also cheaper and the first to be ready in every fab in the world.

I believe that Intel will not use the HP process at 14nm for the Mobile Broadwell. It will most probably use the Standard/Low process and then use the HP for the Desktop and Server parts.

 

[NostaSeronx]

TSMC -> 120 CPP, 96 M1, 2D Routing
IBM/GF/Samsung -> 114 CPP, 90 M1, 2D Routing
Intel -> 90 CPP, 90 M1, 1D Routing

For 28-nm and "22-nm." Looking for Idsat/Ioff will take more than a couple hours to find for all. FinFETs help with CPP but actually ruin Lgate. TSMC/Common Platform in the LP/ULP area are actually more dense than Intel. I can't find a lot for GlobalFoundries SOI 28-nm(28SHP/28CUSTOM), only that it uses SiGe and SiC.

 

[Khato]

For 28-nm and "22-nm." Looking for Idsat/Ioff will take more than a couple hours to find for all. FinFETs help with CPP but actually ruin Lgate. TSMC/Common Platform in the LP/ULP area are actually more dense than Intel. I can't find a lot for GlobalFoundries SOI 28-nm(28SHP/28CUSTOM), only that it uses SiGe and SiC.

The majority of the current process information can still be found in this chart on realworldtech. It's missing Intel's 22nm process, but that's about it. So unfortunately the only data we have for Intel's 22nm drive currents are for the SoC process at 0.75V and hence aren't really comparable to anything else. Well, TSMC did provide numbers for I believe it's their 28nm LP process at 0.8V, which isn't really too fair of a comparison since it's still using poly gates... which is in part why despite the slightly lower voltage Intel's 22nm SoC process still demonstrates far superior drive current at the same leakage by 1.54x/2.3x for NMOS/PMOS. (If you compare previous nodes, Intel has had a marked advantage in drive current compared to the competition for awhile now, especially on the PMOS side.)

 

[TuxDave]

But if what AtenRa says is true how can it be? I mean, he said it'd give higher density but not as much scaling as before, so if what you say is true he'd have to be wrong. And I don't see anything that sounds wrong with his explanation.

I'm not sure why anyone has to be wrong. AtenRa is saying the more you shrink physical dimensions you can potentially achieve higher density. In a terrible analogy, if you had a goal of increasing the weight you can lift, there's multiple muscles that can be improved to hit your year over year goals. But you don't need to improve EVERYTHING to hit your goal. Maybe you had skinny legs and you really should've targeted that more than anything else. But if you strengthened your leg and whatever else muscle on TOP of that, sure you'll probably lift even MORE than if you just worked on your legs.

Or something like that...
/not a fitness expert

 

[Exophase]

I'm not sure why anyone has to be wrong. AtenRa is saying the more you shrink physical dimensions you can potentially achieve higher density. In a terrible analogy, if you had a goal of increasing the weight you can lift, there's multiple muscles that can be improved to hit your year over year goals. But you don't need to improve EVERYTHING to hit your goal. Maybe you had skinny legs and you really should've targeted that more than anything else. But if you strengthened your leg and whatever else muscle on TOP of that, sure you'll probably lift even MORE than if you just worked on your legs.

Or something like that...
/not a fitness expert

He said that based on what's known about the geometry it can still scale lower but not as well as previous nodes, which is going to be true unless nothing in your design is limited by the critical parameter that doesn't scale as well. Intel17 says Intel has commented that it'll scale as well as previous nodes.

These two pieces of information really do actually contradict either.

 

[TuxDave]

He said that based on what's known about the geometry it can still scale lower but not as well as previous nodes, which is going to be true unless nothing in your design is limited by the critical parameter that doesn't scale as well. Intel17 says Intel has commented that it'll scale as well as previous nodes.

These two pieces of information really do actually contradict either.

Maybe I'm misunderstanding AtenRa's post but I don't see that bolded statement.

 

[Exophase]

Maybe I'm misunderstanding AtenRa's post but I don't see that bolded statement.

He said this:

So, even if you keep the same Metal Pitch, if your Gate Pitch is smaller then you will get higher density. It would be much higher if you had both but still it will give you higher density than before.

Are you still not seeing it? He said if you decrease M1 pitch (which is what previous nodes did, did they not?) then you'd get a greater density improvement, while Intel allegedly says they get the same density improvement w/o improving M1 pitch.

 

[Arachnotronic]

He said this:



Are you still not seeing it? He said if you decrease M1 pitch (which is what previous nodes did, did they not?) then you'd get a greater density improvement, while Intel allegedly says they get the same density improvement w/o improving M1 pitch.

Exophase,

No, no. At 14nm M1 pitch is improved from 80nm -> 64nm from the 22nm node. My point is that at 22nm Intel had an 80nm M1 pitch, but at 20nm TSMC has a 64nm M1 pitch.

 

[TuxDave]

Are you still not seeing it? He said if you decrease M1 pitch (which is what previous nodes did, did they not?) then you'd get a greater density improvement, while Intel allegedly says they get the same density improvement w/o improving M1 pitch.

And I've been trying to tell you that there's numerous paths to better density.

(and then there's Intel17's comment)

 

[AtenRa]

OK lets see,

As Intel17 have said, Intel will have lower Metal and Gate pitch at 14nm over 22nm. So most probably they will have almost 2x higher density.

Glofo and TSMC at 14nm will keep the same Metal Pitch of the 20nm (64nm) and will only use a smaller Gate Pitch. That will still give them higher density than 20nm process but not in the order of 2x like they will have from 28nm to 20nm.

 

[Exophase]

Exophase,

No, no. At 14nm M1 pitch is improved from 80nm -> 64nm from the 22nm node. My point is that at 22nm Intel had an 80nm M1 pitch, but at 20nm TSMC has a 64nm M1 pitch.

Okay, I guess I totally missed that. Would you happen to know what it was at 32nm? At any rate, if the M1 pitch doesn't decrease enough (sqrt(2)) from 22nm to 14nm then any parts circuitry bound by M1 pitch can't increase 2x, is that incorrect? Or is there simply nothing in a design with such a bound?

And I've been trying to tell you that there's numerous paths to better density.

(and then there's Intel17's comment)

And I've been trying to tell you that I'm not disputing that they'll still have a density improvement, but if all metrics don't improve as much as they did before it can't be as good of an improvement.

 

[zir_blazer]

Any site that covers the semiconductor industry with articles explaining how stuff works and the like? There are tons of Hardware reviews sites, but few, if any, talks about the manufacturing part of this business. So I never got where people got that data from.

 

[Exophase]

For what it's worth, TSMC's claim for density improvement from 20nm to 16nm is 1.1x. But I don't think there's information on how much gate pitch changes.

 

[AtenRa]

Any site that covers the semiconductor industry with articles explaining how stuff works and the like? There are tons of Hardware reviews sites, but few, if any, talks about the manufacturing part of this business. So I never got where people got that data from.

As Idontcare would say, you can read the "Handbook of Semiconductor Manufacturing Technology" second edition by Robert Doering and Yoshio Nishi

 

[TuxDave]

And I've been trying to tell you that I'm not disputing that they'll still have a density improvement, but if all metrics don't improve as much as they did before it can't be as good of an improvement.

If you still come to this conclusion even after I say "there are numerous paths to better density", I guess what I thought was "obvious" is actually pretty difficult. I personally don't think I can convince you while limiting my participation in this thread. Sorry about that.