I'm confused about Intels 14nm process lead

[krumme]

Just look at Carrizo vs Kaveri. Same 28nm SHP process, but Carrizo is far more dense. Why? Because of the design.

Yes and that even with same pipeline

 

[Arachnotronic]

what about 22nm atoms density?

Intel hasn't publicly disclosed transistor counts for any of the 22nm Atoms.

 

[krumme]

The claim that 1D metals are density neutral or have better density than 2D metals is just a load of bollocks.

1D metals require restricted design rules which decrease effective density, and more metal layers are needed.

Ok. Thanx.

 

[liahos1]

http://www.eetimes.com/document.asp?doc_id=1325787

“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”

 

[ShintaiDK]

http://www.eetimes.com/document.asp?doc_id=1325787

“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”

They need an epic reduction from their 16nm *cough 20nm* to make that happen. But again, its a TSMC statement

Maybe they meant Intels 14nm...

 

[witeken]

Have the transistor count and die size of 14nm Cherry Trail been announced?

It will obviously be smaller than Broxton.

 

[NTMBK]

It will obviously be smaller than Broxton.

Given that they just scaled the same die shot down in Powerpoint for that slide and put no numbers on the scale, I wouldn't read too much into it.

 

[witeken]

http://www.eetimes.com/document.asp?doc_id=1325787

“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”

The title of EETimes is very unprofessional, disappointingly.

First, density. You can do a decent guess by increasing density by 2x, so they could in principle do a decent guess. But it's very unlikely that density will be the same: considering TSMC is already 60% less dense and Intel will do a similar aggressive scaling with 10nm, I say they want to spread (F)UD.

Idem for speed and power. TSMC has already said they it will be their second node with FinFET. If they really think they will catch up to Intel, they will be in for a big surprise with 10nm.

The last important feature, TTM, is also obvious. Just look at the troubles TSMC's having with 20+FF, with FinFET GPUs (if they're still manufactured at TSMC) coming not too much earlier than Intel's 10nm, so the node which they call "10nm" will be just as much behind as 20nm was to 22nm. Which is confirmed by their [late(?)] 2017 production schedule. Not to mention anything about their 7nm (their real 10nm) node.

So
http://www.kitguru.net/wp-content/uploads/2014/07/intel_tech_lead.png

...will still hold true.

Too bad the most important part of the article isn't mentioned: TSMC will not use EUV for 10nm, so they will face substantial multiple patterning yield challenges. We'll see if they can also solve it for the 10nm node like Intel has.

 

[witeken]

Given that they just scaled the same die shot down in Powerpoint for that slide and put no numbers on the scale, I wouldn't read too much into it.

Ashraf Eassa has done an article about it on SA. BT is 102mm² and they confirmed the images were to scale, but the dies are of course no yet disclosed... no duh. I wouldn't have used it if didn't know it was reliable. So Broxton will be ~60mm² or so.

 

[carop]

But it's very unlikely that density will be the same: considering TSMC is already 60% less dense and Intel will do a similar aggressive scaling with 10nm, I say they want to spread (F)UD.

Where is that 60% better density coming from?

 

[witeken]

Where is that 60% better density coming from?

http://forums.anandtech.com/showpost.php?p=37200150&postcount=229

 

[carop]

http://forums.anandtech.com/showpost.php?p=37200150&postcount=229

That figure is from an excellent article from Hiroshige Goto about the complexity of routing with finFETs.

http://pc.watch.impress.co.jp/docs/column/kaigai/20141014_671062.html

When he wrote that article Intel had not disclosed the pithes of its lowest metal layers yet. As such, it was not yet clear whether 52nm was the pitch size of the lowest metal layer or not. So, he used "52(60?)nm" in his figure. In hindsight, he was right.

Intel 14nm:
Contacted gate pitch: 70nm
Metal 0: 56nm
Metal 1: 70nm
Metal 2: 52nm

Reflecting the complexity of routing with finFETs, the pitch of metal 1 is a comparatively relaxed 70nm whereas metal 0 or local interconnect is 56nm and metal 2 is 52nm – presumably to optimize pin access into standard cells.

Where is that 60% better density coming from again? Intel itself claims a 35% density advantage for its 14nm node using the Gate Pitch x Metal Pitch heuristic (70nm x 52nm). However, the relatively tight 52nm metal 2 pitch has so far only shown that that pin access into standard cells is a somewhat complex business with finFETs. Standard cells are below metal 1 and metal 0 layers. And, it is metal 0 that has direct access to the standard cells.

You should read a translation of the article or take a look at it before dragging the name of Hiroshige Goto in the mud.

 

[witeken]

Intel 14nm:
Contacted gate pitch: 70nm
Metal 0: 56nm
Metal 1: 70nm
Metal 2: 52nm

I wonder if anyone (Idontcare) can comment on the choosing of metal layer pitches.

Where is that 60% better density coming from again? Intel itself claims a 35% density advantage for its 14nm node using the Gate Pitch x Metal Pitch heuristic (70nm x 52nm).

35% and 60% are both the same...

Intel was using it as -35% area (= 1/0.65), while I was quoting the density advantage (from those 2 numbers it follows that Intel can put 60% more transistors in a given area).

 

[carop]

Intel was using it as -35% area (= 1/0.65)

Using the metal 3 pitch (if you start counting from 1) in the Gate Pitch x Metal Pitch heuristic is a nice metal 1 marketing trick from Intel. Furthermore, the Gate Pitch x Metal Pitch heuristic conveniently ignores the die cost of 1D metals.

Be that as it may, silicon does not lie. And the silicon data so far failed to support the original 35% better density claim from Intel.

 

[witeken]

Using the metal 3 pitch (if you start counting from 1) in the Gate Pitch x Metal Pitch heuristic is a nice metal 1 marketing trick from Intel. Furthermore, the Gate Pitch x Metal Pitch heuristic conveniently ignores the die cost of 1D metals.

Be that as it may, silicon does not lie. And the silicon data so far failed to support the original 35% better density claim from Intel.

Silicon doesn't lie indeed: that same slide also claimed a 2.2x density improvement (as calculated on SA), which is exactly what we got.

TuxDave or Imported_ats has said that 1D's cost is negligible, IIRC.

 

[Khato]

The claim that 1D metals are density neutral or have better density than 2D metals is just a load of bollocks.

1D metals require restricted design rules which decrease effective density, and more metal layers are needed.

You should really read up on the difference between 1D and 2D layout styles before making such claims. That, and an understanding of design rules would be helpful - gridded design rules are actually markedly simpler than conventional design rules on current leading edge process technology. aka, being limited to a single direction grid is actually a pretty trivial design rule.

Then about the only comparison which has 2D layout coming out ahead would be one that ASML made comparing 2D EUV against 1D multi-pass ArF, where the 1D was about 15% larger. But if you had to design the 2D with the multi-pass ArF design rules that area difference would disappear or possibly reverse.

About the only correct point here is that 1D layout typically does require more metal layers. That's just the expected trade-off though for its many advantages.

 

[carop]

TuxDave or Imported_ats has said that 1D's cost is negligible, IIRC.

As far as the apparent density advantage of Apple A8 is concerned, they appear to have conveniently chosen to keep mum about the die cost of 1D metals.

 

[carop]

You should really read up on the difference between 1D and 2D layout styles before making such claims. That, and an understanding of design rules would be helpful - gridded design rules are actually markedly simpler than conventional design rules on current leading edge process technology. aka, being limited to a single direction grid is actually a pretty trivial design rule.

I have actually read up on the difference between 1D and 2D layouts. 1D metals have several advantages over 2D metals. For example, air gabs in the copper interconnects for logic require regularly spaced 1D line arrays as a design constraint. However, I find it hard to believe that 1D metals are density netural or have better density than 2D metals.

Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.

 

[witeken]

Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.

From what I remember from that discussion, people disagreed because Intel says there's ~no density penalty, and because someone with more knowledge said there isn't.

 

[carop]

From what I remember from that discussion, people disagreed because Intel says there's ~no density penalty, and because someone with more knowledge said there isn't.

Intel claims that 1D metals are density neutral or have better density than 2D metals. However, there are other semiconductor companies who say that 1D metals have a die cost.

Again, silicon does not lie. And, silicon data so far failed to support the original 35% better density claim. I agree with Hans de Vreis that the die cost of 1D metals is one of the factors, if not the only factor, that silicon data so far failed to support the 35% better claim.

On the other hand, Intel makes a lot of claims about a lot of things that are not correct or other semiconductor companies do not agree with. For example, the following comparison is from the STMicroelectronics 10nm FD-SOI IEDM 2014 paper.

[13] is Intel 22nm@VLSI2012
[14] is Intel 22nm SoC@IEDM2012
[15] is TSMC 16nm@IEDM2013

So far as the Intel crowed is concerned, the performance of TSMC 16nm FinFET and STMicroelectronics 10nm FD-SOI barely match the performance of Intel 22nm FinFET. The catch is that there are different ways of normalizing the drive current of FinFET devices, and the way Intel normalizes its drive current makes its drive current 20 - 30% larger. There are device engineers who consider this as cheating and put footnotes to their papers. This is something to bear in mind when benchmarking.

 

[krumme]

Whats your take on if tsmc continue to use 2d routing? Change of design tools they provide?

 

[imported_ats]

Standard cells are below metal 1 and metal 0 layers. And, it is metal 0 that has direct access to the standard cells.

Yeah you basically just went like this with credibility:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
\/

 

[imported_ats]

Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.

Hans either knows or should of known he was making an at best disingenuous argument. Using transistor counts without significant clarification and comparing designs that operate at rather significantly different Fmax and % of logic at Fmax does not for useful comparisons make.

Considering you don't even know how many metal layers standard cells generally use, you might want to back out of this argument space.

 

[Khato]

I have actually read up on the difference between 1D and 2D layouts. 1D metals have several advantages over 2D metals. For example, air gabs in the copper interconnects for logic require regularly spaced 1D line arrays as a design constraint. However, I find it hard to believe that 1D metals are density netural or have better density than 2D metals.

Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.

With respect to silicon data, how about TSMC's 1D experiment on 65nm from a few years ago reducing logic area by 15% - http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=4961&language=E And the potential density increase goes up at the smaller process nodes due to the increasing complexity of 2D routing rules which frequently don't allow as dense of a layout as the process metrics would imply.

Another interesting tidbit from ASML regarding EUV which touches on the subject with respect to 10nm on slides 16-18: http://www.asml.com/doclib/investor...014-05-06_Jefferies_Global_TMT_Conf_Miami.pdf With the interesting point being that they don't see a route to actual 10nm using 2D critical layers, but it can be done 1D. As well, that 1D implementation only sees a 15% area increase over an EUV-enabled 2D - how would that comparison look between 1D and 2D EUV though?

 

[witeken]

Considering you don't even know how many metal layers standard cells generally use, you might want to back out of this argument space.

I don't know either, to be honest..