Just look at Carrizo vs Kaveri. Same 28nm SHP process, but Carrizo is far more dense. Why? Because of the design.
Yes and that even with same pipeline
Just look at Carrizo vs Kaveri. Same 28nm SHP process, but Carrizo is far more dense. Why? Because of the design.
what about 22nm atoms density?
The claim that 1D metals are density neutral or have better density than 2D metals is just a load of bollocks.
1D metals require restricted design rules which decrease effective density, and more metal layers are needed.
http://www.eetimes.com/document.asp?doc_id=1325787
“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”
Have the transistor count and die size of 14nm Cherry Trail been announced?
It will obviously be smaller than Broxton.
http://www.eetimes.com/document.asp?doc_id=1325787
“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”
Given that they just scaled the same die shot down in Powerpoint for that slide and put no numbers on the scale, I wouldn't read too much into it.
But it's very unlikely that density will be the same: considering TSMC is already 60% less dense and Intel will do a similar aggressive scaling with 10nm, I say they want to spread (F)UD.
http://forums.anandtech.com/showpost.php?p=37200150&postcount=229Where is that 60% better density coming from?
I wonder if anyone (Idontcare) can comment on the choosing of metal layer pitches.Intel 14nm:
Contacted gate pitch: 70nm
Metal 0: 56nm
Metal 1: 70nm
Metal 2: 52nm
35% and 60% are both the same...Where is that 60% better density coming from again? Intel itself claims a 35% density advantage for its 14nm node using the Gate Pitch x Metal Pitch heuristic (70nm x 52nm).
Intel was using it as -35% area (= 1/0.65)
Silicon doesn't lie indeed: that same slide also claimed a 2.2x density improvement (as calculated on SA), which is exactly what we got.Using the metal 3 pitch (if you start counting from 1) in the Gate Pitch x Metal Pitch heuristic is a nice metal 1 marketing trick from Intel. Furthermore, the Gate Pitch x Metal Pitch heuristic conveniently ignores the die cost of 1D metals.
Be that as it may, silicon does not lie. And the silicon data so far failed to support the original 35% better density claim from Intel.
The claim that 1D metals are density neutral or have better density than 2D metals is just a load of bollocks.
1D metals require restricted design rules which decrease effective density, and more metal layers are needed.
TuxDave or Imported_ats has said that 1D's cost is negligible, IIRC.
You should really read up on the difference between 1D and 2D layout styles before making such claims. That, and an understanding of design rules would be helpful - gridded design rules are actually markedly simpler than conventional design rules on current leading edge process technology. aka, being limited to a single direction grid is actually a pretty trivial design rule.
Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.
From what I remember from that discussion, people disagreed because Intel says there's ~no density penalty, and because someone with more knowledge said there isn't.
Standard cells are below metal 1 and metal 0 layers. And, it is metal 0 that has direct access to the standard cells.
Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.
I have actually read up on the difference between 1D and 2D layouts. 1D metals have several advantages over 2D metals. For example, air gabs in the copper interconnects for logic require regularly spaced 1D line arrays as a design constraint. However, I find it hard to believe that 1D metals are density netural or have better density than 2D metals.
Hans de Vries tried to make some density comparisons based on available silicon data, and was shouted down by the Intel crowed. I do not agree with all of his conclusions, but I agree with his basic argument that 1D vs 2D metals should be taken into consideration because silicon data so far failed to support the 35% better density claim from Intel.
I don't know either, to be honest..Considering you don't even know how many metal layers standard cells generally use, you might want to back out of this argument space.