Hans either knows or should of known he was making an at best disingenuous argument. Using transistor counts without significant clarification and comparing designs that operate at rather significantly different Fmax and % of logic at Fmax does not for useful comparisons make.
I should let Hans answer this, but I believe his basic argument is that Intel has a density disadvantage because it is using 1D routing. Transistor counts follow from his 1D vs 2D routing argument. He even asked whether Intel would go back to 2D routing. I do not think Intel would even consider going back to 2D routing again, but I agree that 1D vs 2D routing should be a factor for explaining the density disadvantage.
Considering you don't even know how many metal layers standard cells generally use, you might want to back out of this argument space.
As far as I know, The first-level metal is instrumental for intracell routing because it can freely traverse layout items on any other conducting layer, can connect to all silicon layers with no detour, and acts as gateway to all metal layers above. Therefore, I believe using the metal 3 pitch in the Gate Pitch x Metal Pitch (70nm x 56nm) heuristic has to be justified.
Again, silicon does not lie. When, if at all, Intel discloses the transistor count and die size of its Cherry Trail, I expect that 1D vs 2D layouts will have to be considered further. So, there will be further discussions on credibilities, nosedives, etc ...