I'm not sure if everyone calls them "races" - it might be a local thing to our design team. It's normally called a "hold time violation".
Anyway, the idea is that you have two latches back to back with very little logic in between them, and, as usual both of these latches are latched by a clock signal. As temperature decreases, silicon CMOS FET's get quite a bit faster, but wires don't improve as much (more technically: R gets better, but C is basically a constant, so your RC time constant decreases, but not as much as the FET transistor's Idsat increases due to the improvement in 'mean free path' from the temperature reduction). As you lower the temperature the clock signal doesn't really improve much with decreasing temperature because a clock signal is (in every design that I have seen) a massively RC dominated signal, so while the transistors generating the signal improve, the RC time constant doesn't much and the edge rate of the signal doesn't improve much either. Meanwhile the logic path of the signal running from one latch to the next improves significantly.
Now imagine that you have the two latches connected back to back (output of one, tied directly to the input of another) and they both receive the rising edge of a clock signal simulataneously. The input to the first latch goes to the output of the latch. Meanwhile, the clock, which is not an instaneously switching event like you see in books but is actually a signal that takes a while to rise from 0 to 1 (and back down again), is switching away. When it gets high enough, the latch closes. But the slope of the clock hasn't improved as much as the delay of the logic as the temperature goes down, so there's a 'race' can the second latch close before the signal from the first latch arrives. If the signal 'wins' then the second latch loses it's correct value and is replaced with the value that should still be stuck in the first latch. This is bad, and is what I was referring to. Ideally, the clock should always win the race. Normally designers take races into account, and so there are checks to make sure that the logic delay is longer than the time it takes to close the latch again. But fixing a race on one latch can often mean slowing down some other path, so there are limits to what kind of efforts you want to go through to make sure that a race never happens.
I actually asked around to see what other designers thought about the likelihood of temperature dependent races affecting the ability of the CPU to operate at extremely low temperatues. So my musing that these would cause a failure is probably wrong. Intel designers agreed that the PLL and the FSB would be the two most likely problems that you would run into.